[RESEND RFC PATCH v4 5/5] phy: rockchip-pcie: Adjust read mask and write

[Geraldo Nascimento]

On Fri, Jun 13, 2025 at 03:20:56PM -0500, Bjorn Helgaas wrote:
> On Fri, Jun 13, 2025 at 12:06:28PM -0300, Geraldo Nascimento wrote:
> > Section 17.6.10 of the RK3399 TRM "PCIe PIPE PHY registers Description"
> > defines asynchronous strobe TEST_WRITE which should be enabled then
> > disabled and seems to have been copy-pasted as of current. Adjust it.
> > While at it, adjust read mask which should be the same as write mask.
> 
> Not a PCI patch, but "adjust" doesn't tell us what's happening.
> 
> From reading the patch, I assume that since PHY_CFG_WR_ENABLE and
> PHY_CFG_WR_DISABLE were both defined to be 1, this code:
> 
>         regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
>                      HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
>                                    PHY_CFG_WR_MASK,
>                                    PHY_CFG_WR_SHIFT));
> 
> actually left something *enabled* when it meant to disable it.
> 
> Maybe the subject/commit log could say something about actually
> disabling whatever this is instead of leaving it enabled?
> 
> PHY_CFG_RD_MASK appears unused, so maybe it should be just removed.

Your line of reasoning is correct regarding the TEST_WRITE async strobe
register, and there's a picture of the flow in Section 17.5.3
(PCIe PHY Configuration) of the RK3399 TRM, Part 2.

I'll make sure to be more clear in the commit message.

Regarding PHY_CFG_RD_MASK, yes, it is unused AFAICT and can be removed.
It's leftover from BSP where the debugging function phy_rd_cfg exists.

Thanks,
Geraldo Nascimento