[RFC PATCH 2/6] arm64: Support ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION

[Jonathan Cameron]

On Sat, 29 Mar 2025 15:14:14 +0800
Yicong Yang <yangyicong at huawei.com> wrote:

> On 2025/3/29 2:22, Catalin Marinas wrote:
> > On Thu, Mar 20, 2025 at 05:41:14PM +0000, Jonathan Cameron wrote:  
> >> +struct system_cache_flush_method {
> >> +	int (*invalidate_memregion)(int res_desc,
> >> +				    phys_addr_t start, size_t len);
> >> +};  
> > [...]  
> >> +int cpu_cache_invalidate_memregion(int res_desc, phys_addr_t start, size_t len)
> >> +{
> >> +	guard(spinlock_irqsave)(&scfm_lock);
> >> +	if (!scfm_data)
> >> +		return -EOPNOTSUPP;
> >> +
> >> +	return scfm_data->invalidate_memregion(res_desc, start, len);
> >> +}  
> > 
> > WBINVD on x86 deals with the CPU caches as well. Even the API naming in
> > Linux implies CPU caches. IIUC, devices registering to the above on Arm
> > SoCs can only deal with system caches. Is it sufficient?
> >   
> 
> The device driver who register this method should handle this. If the
> hardware support maintaining the coherency among the system, for example
> on system cache invalidation the hardware is also able to invalidate the
> involved cachelines on all the subordinate caches (L1/L2/etc, by back
> invalidate snoop or other ways), then software don't need to invalidate
> the non-system cache explicitly. Otherwise the driver need to explicitly
> invalidate the non-system cache explicitly in their
> scfm_data::invalidate_memregion() method. Here in the generally code we
> simply don't know the capability of the hardware.

Coming to this a little late.  It would definitely be helpful to understand
whether other hardware implementations where this is relevant (e.g. CXL
capable systems) do require explicit flushes of the caches nearer the
CPU and any dance that they need in that case to ensure no race conditions
leave stale lines.

The PSCI spec (that never was) did allow for reporting that it was necessary
to stop all traffic prior to flushes, but that is crazy to support and
someone built the wrong system if they need to do that under even
vaguely normal software flows.

Jonathan
 
> 
> Thanks.
>