[PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree

[Ryan Chen]

> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device
> tree
> 
> On 12/06/2025 12:09, Ryan Chen wrote:
> > +
> > +	soc0: soc at 10000000 {
> > +		compatible = "simple-bus";
> > +		reg = <0x0 0x10000000 0x10000000>;
> > +		#address-cells = <2>;
> > +		#size-cells = <1>;
> > +		ranges;
> > +
> > +		syscon0: syscon at 12c02000 {
> > +			compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
> 
> This makes no sense - no children here.
> 
> > +			reg = <0x0 0x12c02000 0x1000>;
> > +			ranges = <0x0 0x0 0 0x12c02000 0x1000>;
> 
> Neither this.
> 
> > +			#address-cells = <2>;
> > +			#size-cells = <1>;
> 
> Nor this.


I will add by following. 
                 syscon0: syscon at 12c02000 {
                        compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
                        reg = <0x0 0x12c02000 0x0 0x1000>;
                        ranges = <0x0 0x0 0 0x12c02000 0 0x1000>;
                        #address-cells = <2>;
                        #size-cells = <2>;
                        #clock-cells = <1>;
                        #reset-cells = <1>;

                        silicon-id at 0 {
                                compatible = "aspeed,ast2700-silicon-id", "aspeed,silicon-id";
                                reg = <0 0x0 0 0x4>;
                        };

                        scu_ic0: interrupt-controller at 1D0 {
                                #interrupt-cells = <1>;
                                compatible = "aspeed,ast2700-scu-ic0";
                                reg = <0 0x1d0 0 0xc>;
                                interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-controller;
                        };

                        scu_ic1: interrupt-controller at 1E0 {
                                #interrupt-cells = <1>;
                                compatible = "aspeed,ast2700-scu-ic1";
                                reg = <0 0x1e0 0 0xc>;
                                interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-controller;
                        };

                        pinctrl0: pinctrl at 400 {
                                compatible = "aspeed,ast2700-soc0-pinctrl";
                                reg = <0 0x400 0 0x600>;
                        };
                };

              syscon1: syscon at 14c02000 {
                        compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd";
                        reg = <0x0 0x14c02000 0x0 0x1000>;
                        ranges = <0x0 0x0 0x0 0x14c02000 0x0 0x1000>;
                        #address-cells = <2>;
                        #size-cells = <2>;
                        #clock-cells = <1>;
                        #reset-cells = <1>;

                        scu_ic2: interrupt-controller at 100 {
                                #interrupt-cells = <1>;
                                compatible = "aspeed,ast2700-scu-ic2";
                                reg = <0 0x100 0 0x8>;
                                interrupts-extended = <&intc1_5 0>;
                                interrupt-controller;
                        };

                        scu_ic3: interrupt-controller at 108 {
                                #interrupt-cells = <1>;
                                compatible = "aspeed,ast2700-scu-ic3";
                                reg = <0 0x108 0 0x8>;
                                interrupts-extended = <&intc1_5 26>;
                                interrupt-controller;
                        };

                        pinctrl1: pinctrl at 400 {
                                compatible = "aspeed,ast2700-soc1-pinctrl";
                                reg = <0x0 0x400 0x0 0x100>;
                        };
                };

> 
> 
> Best regards,
> Krzysztof