[PATCH v23 1/4] arm64/sysreg: Add BRBE registers and fields
Rob Herring
robh at kernel.org
Thu Jun 12 13:20:28 PDT 2025
On Thu, Jun 12, 2025 at 2:46 PM Adam Young
<admiyo at amperemail.onmicrosoft.com> wrote:
>
> tested-by: Adam Young<admiyo at os.amperecomputing.com>
Thanks, I assume this is for patch 1, 2, and 4 at least because just
this patch does nothing on its own.
Note that on the mail lists, you should not top-post, but reply below
the quoted message.
Rob
>
> Built and run on a BRBE capable machine.
>
> Built userland perf tool
>
> can run
>
> perf record --branch-filter any,save_type,u true
>
> as well as
>
> perf record --branch-filter any,save_type,u ./sort
>
> And will generate a perf.data file.
>
> The mechanism applies cleanly and produced what looks like sane output.
>
>
> On 6/11/25 14:01, Rob Herring (Arm) wrote:
> > From: Anshuman Khandual <anshuman.khandual at arm.com>
> >
> > This patch adds definitions related to the Branch Record Buffer Extension
> > (BRBE) as per ARM DDI 0487K.a. These will be used by KVM and a BRBE driver
> > in subsequent patches.
> >
> > Some existing BRBE definitions in asm/sysreg.h are replaced with equivalent
> > generated definitions.
> >
> > Cc: Marc Zyngier <maz at kernel.org>
> > Reviewed-by: Mark Brown <broonie at kernel.org>
> > Signed-off-by: Anshuman Khandual <anshuman.khandual at arm.com>
> > Signed-off-by: Mark Rutland <mark.rutland at arm.com>
> > Tested-by: James Clark <james.clark at linaro.org>
> > Acked-by: Will Deacon <will at kernel.org>
> > Signed-off-by: "Rob Herring (Arm)" <robh at kernel.org>
> > ---
> > v19:
> > - split BRBINF.CC field into mantissa and exponent
> > ---
> > arch/arm64/include/asm/sysreg.h | 16 ++---
> > arch/arm64/tools/sysreg | 132 ++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 138 insertions(+), 10 deletions(-)
> >
> > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> > index f1bb0d10c39a..ef76a4b9e240 100644
> > --- a/arch/arm64/include/asm/sysreg.h
> > +++ b/arch/arm64/include/asm/sysreg.h
> > @@ -202,16 +202,8 @@
> > #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
> >
> > #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
> > -#define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
> > #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
> > -#define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
> > #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
> > -#define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
> > -#define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
> > -
> > -#define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
> > -#define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
> > -#define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
> >
> > #define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
> > #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
> > @@ -277,8 +269,6 @@
> > /* ETM */
> > #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
> >
> > -#define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0)
> > -
> > #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
> > #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
> > #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
> > @@ -821,6 +811,12 @@
> > #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
> > #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
> >
> > +/*
> > + * BRBE Instructions
> > + */
> > +#define BRB_IALL_INSN __emit_inst(0xd5000000 | OP_BRB_IALL | (0x1f))
> > +#define BRB_INJ_INSN __emit_inst(0xd5000000 | OP_BRB_INJ | (0x1f))
> > +
> > /* Common SCTLR_ELx flags. */
> > #define SCTLR_ELx_ENTP2 (BIT(60))
> > #define SCTLR_ELx_DSSBS (BIT(44))
> > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> > index 8a8cf6874298..81c4e214ba33 100644
> > --- a/arch/arm64/tools/sysreg
> > +++ b/arch/arm64/tools/sysreg
> > @@ -1329,6 +1329,138 @@ UnsignedEnum 3:0 MTEPERM
> > EndEnum
> > EndSysreg
> >
> > +
> > +SysregFields BRBINFx_EL1
> > +Res0 63:47
> > +Field 46 CCU
> > +Field 45:40 CC_EXP
> > +Field 39:32 CC_MANT
> > +Res0 31:18
> > +Field 17 LASTFAILED
> > +Field 16 T
> > +Res0 15:14
> > +Enum 13:8 TYPE
> > + 0b000000 DIRECT_UNCOND
> > + 0b000001 INDIRECT
> > + 0b000010 DIRECT_LINK
> > + 0b000011 INDIRECT_LINK
> > + 0b000101 RET
> > + 0b000111 ERET
> > + 0b001000 DIRECT_COND
> > + 0b100001 DEBUG_HALT
> > + 0b100010 CALL
> > + 0b100011 TRAP
> > + 0b100100 SERROR
> > + 0b100110 INSN_DEBUG
> > + 0b100111 DATA_DEBUG
> > + 0b101010 ALIGN_FAULT
> > + 0b101011 INSN_FAULT
> > + 0b101100 DATA_FAULT
> > + 0b101110 IRQ
> > + 0b101111 FIQ
> > + 0b110000 IMPDEF_TRAP_EL3
> > + 0b111001 DEBUG_EXIT
> > +EndEnum
> > +Enum 7:6 EL
> > + 0b00 EL0
> > + 0b01 EL1
> > + 0b10 EL2
> > + 0b11 EL3
> > +EndEnum
> > +Field 5 MPRED
> > +Res0 4:2
> > +Enum 1:0 VALID
> > + 0b00 NONE
> > + 0b01 TARGET
> > + 0b10 SOURCE
> > + 0b11 FULL
> > +EndEnum
> > +EndSysregFields
> > +
> > +SysregFields BRBCR_ELx
> > +Res0 63:24
> > +Field 23 EXCEPTION
> > +Field 22 ERTN
> > +Res0 21:10
> > +Field 9 FZPSS
> > +Field 8 FZP
> > +Res0 7
> > +Enum 6:5 TS
> > + 0b01 VIRTUAL
> > + 0b10 GUEST_PHYSICAL
> > + 0b11 PHYSICAL
> > +EndEnum
> > +Field 4 MPRED
> > +Field 3 CC
> > +Res0 2
> > +Field 1 ExBRE
> > +Field 0 E0BRE
> > +EndSysregFields
> > +
> > +Sysreg BRBCR_EL1 2 1 9 0 0
> > +Fields BRBCR_ELx
> > +EndSysreg
> > +
> > +Sysreg BRBFCR_EL1 2 1 9 0 1
> > +Res0 63:30
> > +Enum 29:28 BANK
> > + 0b00 BANK_0
> > + 0b01 BANK_1
> > +EndEnum
> > +Res0 27:23
> > +Field 22 CONDDIR
> > +Field 21 DIRCALL
> > +Field 20 INDCALL
> > +Field 19 RTN
> > +Field 18 INDIRECT
> > +Field 17 DIRECT
> > +Field 16 EnI
> > +Res0 15:8
> > +Field 7 PAUSED
> > +Field 6 LASTFAILED
> > +Res0 5:0
> > +EndSysreg
> > +
> > +Sysreg BRBTS_EL1 2 1 9 0 2
> > +Field 63:0 TS
> > +EndSysreg
> > +
> > +Sysreg BRBINFINJ_EL1 2 1 9 1 0
> > +Fields BRBINFx_EL1
> > +EndSysreg
> > +
> > +Sysreg BRBSRCINJ_EL1 2 1 9 1 1
> > +Field 63:0 ADDRESS
> > +EndSysreg
> > +
> > +Sysreg BRBTGTINJ_EL1 2 1 9 1 2
> > +Field 63:0 ADDRESS
> > +EndSysreg
> > +
> > +Sysreg BRBIDR0_EL1 2 1 9 2 0
> > +Res0 63:16
> > +Enum 15:12 CC
> > + 0b0101 20_BIT
> > +EndEnum
> > +Enum 11:8 FORMAT
> > + 0b0000 FORMAT_0
> > +EndEnum
> > +Enum 7:0 NUMREC
> > + 0b00001000 8
> > + 0b00010000 16
> > + 0b00100000 32
> > + 0b01000000 64
> > +EndEnum
> > +EndSysreg
> > +
> > +Sysreg BRBCR_EL2 2 4 9 0 0
> > +Fields BRBCR_ELx
> > +EndSysreg
> > +
> > +Sysreg BRBCR_EL12 2 5 9 0 0
> > +Fields BRBCR_ELx
> > +EndSysreg
> > +
> > Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4
> > Res0 63:60
> > UnsignedEnum 59:56 F64MM
> >
>
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