[PATCH 1/2] arm64: dts: lg: Refactor common LG1312 and LG1313 parts
Rob Herring (Arm)
robh at kernel.org
Mon Jun 9 14:54:56 PDT 2025
The LG1312 and LG1313 DT are almost identical with the exception of the
ethernet node. Refactor the common parts into a separate .dtsi file and
include it.
Signed-off-by: Rob Herring (Arm) <robh at kernel.org>
---
arch/arm64/boot/dts/lg/lg1312.dtsi | 324 +-----------------------------------
arch/arm64/boot/dts/lg/lg1313.dtsi | 324 +-----------------------------------
arch/arm64/boot/dts/lg/lg131x.dtsi | 333 +++++++++++++++++++++++++++++++++++++
3 files changed, 337 insertions(+), 644 deletions(-)
diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi
index bb0bcc6875dc..e83fdc92621e 100644
--- a/arch/arm64/boot/dts/lg/lg1312.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
@@ -5,103 +5,12 @@
* Copyright (C) 2016, LG Electronics
*/
-#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
+#include "lg131x.dtsi"
+/ {
compatible = "lge,lg1312";
- interrupt-parent = <&gic>;
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu0: cpu at 0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x0>;
- next-level-cache = <&L2_0>;
- };
- cpu1: cpu at 1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x1>;
- enable-method = "psci";
- next-level-cache = <&L2_0>;
- };
- cpu2: cpu at 2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x2>;
- enable-method = "psci";
- next-level-cache = <&L2_0>;
- };
- cpu3: cpu at 3 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x3>;
- enable-method = "psci";
- next-level-cache = <&L2_0>;
- };
- L2_0: l2-cache0 {
- compatible = "cache";
- cache-level = <2>;
- cache-unified;
- };
- };
-
- psci {
- compatible = "arm,psci-0.2", "arm,psci";
- method = "smc";
- cpu_suspend = <0x84000001>;
- cpu_off = <0x84000002>;
- cpu_on = <0x84000003>;
- };
-
- gic: interrupt-controller at c0001000 {
- #interrupt-cells = <3>;
- compatible = "arm,gic-400";
- interrupt-controller;
- reg = <0x0 0xc0001000 0x1000>,
- <0x0 0xc0002000 0x2000>,
- <0x0 0xc0004000 0x2000>,
- <0x0 0xc0006000 0x2000>;
- };
-
- pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>,
- <&cpu1>,
- <&cpu2>,
- <&cpu3>;
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
- IRQ_TYPE_LEVEL_LOW)>;
- };
-
- clk_bus: clk_bus {
- #clock-cells = <0>;
-
- compatible = "fixed-clock";
- clock-frequency = <198000000>;
- clock-output-names = "BUSCLK";
- };
soc {
#address-cells = <2>;
@@ -122,233 +31,4 @@ eth0: ethernet at c1b00000 {
mac-address = [ 00 00 00 00 00 00 ];
};
};
-
- amba {
- #address-cells = <2>;
- #size-cells = <1>;
-
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
-
- timers: timer at fd100000 {
- compatible = "arm,sp804", "arm,primecell";
- reg = <0x0 0xfd100000 0x1000>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>;
- clock-names = "timer0clk", "timer1clk", "apb_pclk";
- };
- wdog: watchdog at fd200000 {
- compatible = "arm,sp805", "arm,primecell";
- reg = <0x0 0xfd200000 0x1000>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>, <&clk_bus>;
- clock-names = "wdog_clk", "apb_pclk";
- };
- uart0: serial at fe000000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x0 0xfe000000 0x1000>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- uart1: serial at fe100000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x0 0xfe100000 0x1000>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- uart2: serial at fe200000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x0 0xfe200000 0x1000>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- spi0: spi at fe800000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x0 0xfe800000 0x1000>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>, <&clk_bus>;
- clock-names = "sspclk", "apb_pclk";
- };
- spi1: spi at fe900000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x0 0xfe900000 0x1000>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>, <&clk_bus>;
- clock-names = "sspclk", "apb_pclk";
- };
- dmac0: dma-controller at c1128000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xc1128000 0x1000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- };
- gpio0: gpio at fd400000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd400000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio1: gpio at fd410000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd410000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio2: gpio at fd420000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd420000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio3: gpio at fd430000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd430000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- };
- gpio4: gpio at fd440000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd440000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio5: gpio at fd450000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd450000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio6: gpio at fd460000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd460000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio7: gpio at fd470000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd470000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio8: gpio at fd480000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd480000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio9: gpio at fd490000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd490000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio10: gpio at fd4a0000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd4a0000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio11: gpio at fd4b0000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd4b0000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- };
- gpio12: gpio at fd4c0000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd4c0000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio13: gpio at fd4d0000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd4d0000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio14: gpio at fd4e0000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd4e0000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio15: gpio at fd4f0000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd4f0000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio16: gpio at fd500000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd500000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio17: gpio at fd510000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd510000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- };
- };
};
diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
index c07d670bc465..92fa5694cad1 100644
--- a/arch/arm64/boot/dts/lg/lg1313.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
@@ -5,103 +5,12 @@
* Copyright (C) 2016, LG Electronics
*/
-#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
+#include "lg131x.dtsi"
+/ {
compatible = "lge,lg1313";
- interrupt-parent = <&gic>;
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu0: cpu at 0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x0>;
- next-level-cache = <&L2_0>;
- };
- cpu1: cpu at 1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x1>;
- enable-method = "psci";
- next-level-cache = <&L2_0>;
- };
- cpu2: cpu at 2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x2>;
- enable-method = "psci";
- next-level-cache = <&L2_0>;
- };
- cpu3: cpu at 3 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x3>;
- enable-method = "psci";
- next-level-cache = <&L2_0>;
- };
- L2_0: l2-cache0 {
- compatible = "cache";
- cache-level = <2>;
- cache-unified;
- };
- };
-
- psci {
- compatible = "arm,psci-0.2", "arm,psci";
- method = "smc";
- cpu_suspend = <0x84000001>;
- cpu_off = <0x84000002>;
- cpu_on = <0x84000003>;
- };
-
- gic: interrupt-controller at c0001000 {
- #interrupt-cells = <3>;
- compatible = "arm,gic-400";
- interrupt-controller;
- reg = <0x0 0xc0001000 0x1000>,
- <0x0 0xc0002000 0x2000>,
- <0x0 0xc0004000 0x2000>,
- <0x0 0xc0006000 0x2000>;
- };
-
- pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>,
- <&cpu1>,
- <&cpu2>,
- <&cpu3>;
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
- IRQ_TYPE_LEVEL_LOW)>;
- };
-
- clk_bus: clk_bus {
- #clock-cells = <0>;
-
- compatible = "fixed-clock";
- clock-frequency = <198000000>;
- clock-output-names = "BUSCLK";
- };
soc {
#address-cells = <2>;
@@ -122,233 +31,4 @@ eth0: ethernet at c3700000 {
mac-address = [ 00 00 00 00 00 00 ];
};
};
-
- amba {
- #address-cells = <2>;
- #size-cells = <1>;
-
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
-
- timers: timer at fd100000 {
- compatible = "arm,sp804", "arm,primecell";
- reg = <0x0 0xfd100000 0x1000>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>;
- clock-names = "timer0clk", "timer1clk", "apb_pclk";
- };
- wdog: watchdog at fd200000 {
- compatible = "arm,sp805", "arm,primecell";
- reg = <0x0 0xfd200000 0x1000>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>, <&clk_bus>;
- clock-names = "wdog_clk", "apb_pclk";
- };
- uart0: serial at fe000000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x0 0xfe000000 0x1000>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- uart1: serial at fe100000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x0 0xfe100000 0x1000>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- uart2: serial at fe200000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x0 0xfe200000 0x1000>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- spi0: spi at fe800000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x0 0xfe800000 0x1000>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>, <&clk_bus>;
- clock-names = "sspclk", "apb_pclk";
- };
- spi1: spi at fe900000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x0 0xfe900000 0x1000>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>, <&clk_bus>;
- clock-names = "sspclk", "apb_pclk";
- };
- dmac0: dma-controller at c1128000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xc1128000 0x1000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- };
- gpio0: gpio at fd400000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd400000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio1: gpio at fd410000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd410000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio2: gpio at fd420000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd420000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio3: gpio at fd430000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd430000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- };
- gpio4: gpio at fd440000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd440000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio5: gpio at fd450000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd450000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio6: gpio at fd460000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd460000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio7: gpio at fd470000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd470000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio8: gpio at fd480000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd480000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio9: gpio at fd490000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd490000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio10: gpio at fd4a0000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd4a0000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio11: gpio at fd4b0000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd4b0000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- };
- gpio12: gpio at fd4c0000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd4c0000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio13: gpio at fd4d0000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd4d0000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio14: gpio at fd4e0000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd4e0000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio15: gpio at fd4f0000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd4f0000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio16: gpio at fd500000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd500000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
- gpio17: gpio at fd510000 {
- #gpio-cells = <2>;
- compatible = "arm,pl061", "arm,primecell";
- gpio-controller;
- reg = <0x0 0xfd510000 0x1000>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
- };
- };
};
diff --git a/arch/arm64/boot/dts/lg/lg131x.dtsi b/arch/arm64/boot/dts/lg/lg131x.dtsi
new file mode 100644
index 000000000000..dc4229bd9ebb
--- /dev/null
+++ b/arch/arm64/boot/dts/lg/lg131x.dtsi
@@ -0,0 +1,333 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for lg131x SoCs
+ *
+ * Copyright (C) 2016, LG Electronics
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ next-level-cache = <&L2_0>;
+ };
+ cpu1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+ cpu2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+ cpu3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2", "arm,psci";
+ method = "smc";
+ cpu_suspend = <0x84000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0x84000003>;
+ };
+
+ gic: interrupt-controller at c0001000 {
+ #interrupt-cells = <3>;
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ reg = <0x0 0xc0001000 0x1000>,
+ <0x0 0xc0002000 0x2000>,
+ <0x0 0xc0004000 0x2000>,
+ <0x0 0xc0006000 0x2000>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>,
+ <&cpu2>,
+ <&cpu3>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ clk_bus: clk_bus {
+ #clock-cells = <0>;
+
+ compatible = "fixed-clock";
+ clock-frequency = <198000000>;
+ clock-output-names = "BUSCLK";
+ };
+
+ amba {
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ timers: timer at fd100000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x0 0xfd100000 0x1000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
+ };
+ wdog: watchdog at fd200000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x0 0xfd200000 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_bus>, <&clk_bus>;
+ clock-names = "wdog_clk", "apb_pclk";
+ };
+ uart0: serial at fe000000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfe000000 0x1000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ uart1: serial at fe100000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfe100000 0x1000>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ uart2: serial at fe200000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfe200000 0x1000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ spi0: spi at fe800000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xfe800000 0x1000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_bus>, <&clk_bus>;
+ clock-names = "sspclk", "apb_pclk";
+ };
+ spi1: spi at fe900000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xfe900000 0x1000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_bus>, <&clk_bus>;
+ clock-names = "sspclk", "apb_pclk";
+ };
+ dmac0: dma-controller at c1128000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xc1128000 0x1000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ };
+ gpio0: gpio at fd400000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd400000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ gpio1: gpio at fd410000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd410000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ gpio2: gpio at fd420000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd420000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ gpio3: gpio at fd430000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd430000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ };
+ gpio4: gpio at fd440000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd440000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ gpio5: gpio at fd450000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd450000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ gpio6: gpio at fd460000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd460000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ gpio7: gpio at fd470000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd470000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ gpio8: gpio at fd480000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd480000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ gpio9: gpio at fd490000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd490000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ gpio10: gpio at fd4a0000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd4a0000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ gpio11: gpio at fd4b0000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd4b0000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ };
+ gpio12: gpio at fd4c0000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd4c0000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ gpio13: gpio at fd4d0000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd4d0000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ gpio14: gpio at fd4e0000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd4e0000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ gpio15: gpio at fd4f0000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd4f0000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ gpio16: gpio at fd500000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd500000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ gpio17: gpio at fd510000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x0 0xfd510000 0x1000>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ };
+ };
+};
--
2.47.2
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