[PATCH] arm64: dts: ti: k3-am642-evm-pcie0-ep: Add boot phase tag to "pcie0_ep"

[Nishanth Menon]

On 14:24-20250609, Hrushikesh Salunke wrote:
> AM64X SoC has one instance of PCIe PCIe0. To support PCIe boot on
> AM64X SoC PCIe0 instance needs to be in endpoint mode and it needs to
> be functional at all stages of PCIe boot process. Thus add the
> "bootph-all" boot phase tag to "pcie0_ep" device tree node.
> 
> Signed-off-by: Hrushikesh Salunke <h-salunke at ti.com>
> ---
> This patch is based on commit
> 475c850a7fdd Add linux-next specific files for 20250606
> 
>  arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
> index 432751774853..268a3183753e 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
> @@ -30,6 +30,7 @@ &cbass_main {
>  	interrupt-parent = <&gic500>;
>  
>  	pcie0_ep: pcie-ep at f102000 {
> +		bootph-all;

For new entries being added, please follow
Documentation/devicetree/bindings/dts-coding-style.rst

for guidance, look at where bootph is being added in more recent patches.

>  		compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
>  		reg = <0x00 0x0f102000 0x00 0x1000>,
>  		      <0x00 0x0f100000 0x00 0x400>,
> -- 
> 2.34.1
> 

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D