[PATCH v2 3/3] arm64: dts: renesas: r8a779g3: Describe split PCIe clock on V4H Sparrow Hawk
Manivannan Sadhasivam
manivannan.sadhasivam at linaro.org
Wed Jun 4 10:31:02 PDT 2025
On Wed, Jun 04, 2025 at 11:24:17AM +0200, Geert Uytterhoeven wrote:
> Hi Marek,
>
> On Sat, 31 May 2025 at 00:55, Marek Vasut
> <marek.vasut+renesas at mailbox.org> wrote:
> > The V4H Sparrow Hawk board supplies PCIe controller input clock and PCIe
> > bus clock from separate outputs of Renesas 9FGV0441 clock generator chip.
> > Describe this split bus configuration in the board DT. The topology looks
> > as follows:
> >
> > ____________ _____________
> > | R-Car PCIe | | PCIe device |
> > | | | |
> > | PCIe RX<|==================|>PCIe TX |
> > | PCIe TX<|==================|>PCIe RX |
> > | | | |
> > | PCIe CLK<|======.. ..======|>PCIe CLK |
> > '------------' || || '-------------'
> > || ||
> > ____________ || ||
> > | 9FGV0441 | || ||
> > | | || ||
> > | CLK DIF0<|======'' ||
> > | CLK DIF1<|==========''
> > | CLK DIF2<|
> > | CLK DIF3<|
> > '------------'
> >
> > Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
>
> Thanks for your patch!
>
> > V2: Use pciec0_rp/pciec1_rp phandles to refer to root port moved to core r8a779g0.dtsi
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas at glider.be>
>
> I understand this has a hard dependency on [PATCH v2 1/3] (and on
> enabling CONFIG_PCI_PWRCTRL_SLOT), so I cannot apply this before that
> patch is upstream?
>
TBH, this patch is describing the binding properly. So even though the driver
change is necessary to make the device functional, I don't see it as a hard
dependency. But since people care about functionality, if both driver and DTS
changes go into the same release, it should be fine IMO.
- Mani
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