[PATCH v3 1/2] dt-bindings: interrupt-controller: aspeed: Add parent node compatibles and refine documentation

[Ryan Chen]

> Subject: Re: [PATCH v3 1/2] dt-bindings: interrupt-controller: aspeed: Add
> parent node compatibles and refine documentation
> 
> On Tue, Jul 22 2025 at 17:51, Ryan Chen wrote:
> > -        interrupt-controller at 12101b00 {
> > -            compatible = "aspeed,ast2700-intc-ic";
> > -            reg = <0 0x12101b00 0 0x10>;
> > -            #interrupt-cells = <2>;
> > -            interrupt-controller;
> > -            interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> > -                         <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
> > -                         <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
> > -                         <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
> > -                         <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
> > -                         <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
> > +        intc1_0: interrupt-controller at 100 {
> > +          compatible = "aspeed,ast2700-intc-ic";
> > +          reg = <0x0 0x100 0x0 0x10>;
> 
> I doubt that the controller base address is at 0x100 ...
Sorry, besides the interrupt cascade, our interrupt architecture is most like this one.
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/interrupt-controller/marvell%2Ccp110-icu.yaml#L74-L98
and also others
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/mmc/aspeed%2Csdhci.yaml#L83-L107

I don't understand you doubt it, and also we have proven in our internal Linux release.
https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi#L1676-L1730

Could you point out more information what you doubt? And I can provide more information.