[PATCH 1/7] arm64: dts: ti: k3-j721s2-main: Add interrupts property

[Yemike Abhilash Chandra]

Hi Udit,

Thanks for the review.

On 21/07/25 19:40, Kumar, Udit wrote:
> 
> On 7/21/2025 7:37 PM, Kumar, Udit wrote:
>>
>> On 7/14/2025 2:57 PM, Yemike Abhilash Chandra wrote:
>>> Add interrupts property for CDNS CSI2RX. Interrupt IDs are taken from 
>>> the
>>> J721S2 TRM [0].
>>>
>>> Interrupt Line      | Source Interrupt
>>> --------------------|----------------------------
>>> GIC500SS_SPI_IN_153 | CSI_RX_IF1_CSI_ERR_IRQ_0
>>> GIC500SS_SPI_IN_152 | CSI_RX_IF1_CSI_IRQ_0
>>> GIC500SS_SPI_IN_157 | CSI_RX_IF2_CSI_ERR_IRQ_0
>>> GIC500SS_SPI_IN_156 | CSI_RX_IF2_CSI_IRQ_0
>>>
>>> [0]: https://www.ti.com/lit/zip/spruj28
>>>
>>> Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra at ti.com>
>>> ---
>>>   arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 6 ++++++
>>>   1 file changed, 6 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi 
>>> b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>>> index 62f45377a2c9..6f32a2b0c40c 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>>> @@ -1248,6 +1248,9 @@ ti_csi2rx0: ticsi2rx at 4500000 {
>>>           cdns_csi2rx0: csi-bridge at 4504000 {
>>>               compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
>>>               reg = <0x00 0x04504000 0x00 0x1000>;
>>> +            interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
>>> +                     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
>>
>> Just cosmetic thing, if you are doing v2 then consider 152 first , 
>> followed by 153.
>>
>> Otherwise
>>
>> Reviewed-by: Udit Kumar <u-kumar1 at ti.com>
> 
> 
> Sorry, sent too fast, offset of 32 missing .
> 

 From what I’ve seen, the SPI interrupt IDs on J721S2 start from 0,
so I don’t think we need to subtract the 32 offset.


Interrupt Input Line   Interrupt ID    Source Interrupt
-------------------------------------------------------------
GIC500SS_SPI_IN_00     0               ESM0_ESM_INT_CFG_LVL_0

To confirm this, I’ve latched onto the correct interrupt line, and
my IRQ handler is getting triggered as expected. I’m also seeing the
desired output [0].

Let me know if I might be missing anything.

[0]: 
https://gist.github.com/Yemike-Abhilash-Chandra/f46587ec1ef72671ee31803dd93434b4

Thanks and Regards
Yemike Abhilash Chandra

> 
>>
>>> +            interrupt-names = "error_irq", "irq";
>>>               clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 
>>> 3>,
>>>                   <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>;
>>>               clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
>>> @@ -1301,6 +1304,9 @@ ti_csi2rx1: ticsi2rx at 4510000 {
>>>           cdns_csi2rx1: csi-bridge at 4514000 {
>>>               compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
>>>               reg = <0x00 0x04514000 0x00 0x1000>;
>>> +            interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
>>> +                     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
>>> +            interrupt-names = "error_irq", "irq";
>>>               clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 
>>> 3>,
>>>                   <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>;
>>>               clock-names = "sys_clk", "p_clk", "pixel_if0_clk",