[PATCH v4 0/9] Add SBI v3.0 PMU enhancements
Anup Patel
anup at brainfault.org
Mon Jul 21 20:59:40 PDT 2025
Hi Will,
On Tue, Jul 22, 2025 at 8:45 AM Atish Patra <atishp at rivosinc.com> wrote:
>
> SBI v3.0 specification[1] added two new improvements to the PMU chaper.
> The SBI v3.0 specification is frozen and under public review phase as
> per the RISC-V International guidelines.
>
> 1. Added an additional get_event_info function to query event availablity
> in bulk instead of individual SBI calls for each event. This helps in
> improving the boot time.
>
> 2. Raw event width allowed by the platform is widened to have 56 bits
> with RAW event v2 as per new clarification in the priv ISA[2].
>
> Apart from implementing these new features, this series improves the gpa
> range check in KVM and updates the kvm SBI implementation to SBI v3.0.
>
> The opensbi patches have been merged. This series can be found at [3].
>
> [1] https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0-rc7/riscv-sbi.pdf
> [2] https://github.com/riscv/riscv-isa-manual/issues/1578
> [3] https://github.com/atishp04/linux/tree/b4/pmu_event_info_v4
>
> Signed-off-by: Atish Patra <atishp at rivosinc.com>
> ---
> Changes in v4:
> - Rebased on top of v6.16-rc7
> - Fixed a potential compilation issue in PATCH5.
> - Minor typos fixed PATCH2 and PATCH3.
> - Fixed variable ordering in PATCH6
> - Link to v3: https://lore.kernel.org/r/20250522-pmu_event_info-v3-0-f7bba7fd9cfe@rivosinc.com
>
> Changes in v3:
> - Rebased on top of v6.15-rc7
> - Link to v2: https://lore.kernel.org/r/20250115-pmu_event_info-v2-0-84815b70383b@rivosinc.com
>
> Changes in v2:
> - Dropped PATCH 2 to be taken during rcX.
> - Improved gpa range check validation by introducing a helper function
> and checking the entire range.
> - Link to v1: https://lore.kernel.org/r/20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com
>
> ---
> Atish Patra (9):
> drivers/perf: riscv: Add SBI v3.0 flag
> drivers/perf: riscv: Add raw event v2 support
> RISC-V: KVM: Add support for Raw event v2
> drivers/perf: riscv: Implement PMU event info function
> drivers/perf: riscv: Export PMU event info function
> KVM: Add a helper function to validate vcpu gpa range
> RISC-V: KVM: Use the new gpa range validate helper function
> RISC-V: KVM: Implement get event info function
> RISC-V: KVM: Upgrade the supported SBI version to 3.0
>
> arch/riscv/include/asm/kvm_vcpu_pmu.h | 3 +
> arch/riscv/include/asm/kvm_vcpu_sbi.h | 2 +-
> arch/riscv/include/asm/sbi.h | 13 +++
> arch/riscv/kvm/vcpu_pmu.c | 75 ++++++++++++-
> arch/riscv/kvm/vcpu_sbi_pmu.c | 3 +
> arch/riscv/kvm/vcpu_sbi_sta.c | 6 +-
> drivers/perf/riscv_pmu_sbi.c | 191 +++++++++++++++++++++++++---------
> include/linux/kvm_host.h | 2 +
> include/linux/perf/riscv_pmu.h | 1 +
> virt/kvm/kvm_main.c | 21 ++++
> 10 files changed, 258 insertions(+), 59 deletions(-)
Are you okay with this series going through the KVM RISC-V tree ?
Regards,
Anup
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