[PATCH 6/9] thermal/drivers/mediatek/lvts: Add support for ATP mode
Chen-Yu Tsai
wenst at chromium.org
Mon Jul 21 04:09:45 PDT 2025
On Mon, Jul 21, 2025 at 4:33 PM Laura Nao <laura.nao at collabora.com> wrote:
>
> MT8196/MT6991 uses ATP (Abnormal Temperature Prevention) mode to detect
> abnormal temperature conditions, which involves reading temperature data
> from a dedicated set of registers separate from the ones used for
> immediate and filtered modes.
>
> Add support for ATP mode and its relative registers to ensure accurate
> temperature readings and proper thermal management on MT8196/MT6991
> devices.
>
> Signed-off-by: Laura Nao <laura.nao at collabora.com>
> ---
> drivers/thermal/mediatek/lvts_thermal.c | 34 ++++++++++++++++++++++---
> 1 file changed, 31 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
> index 3c34956e37c1..8f9da0d5b886 100644
> --- a/drivers/thermal/mediatek/lvts_thermal.c
> +++ b/drivers/thermal/mediatek/lvts_thermal.c
> @@ -44,6 +44,10 @@
> #define LVTS_EDATA01(__base) (__base + 0x0058)
> #define LVTS_EDATA02(__base) (__base + 0x005C)
> #define LVTS_EDATA03(__base) (__base + 0x0060)
> +#define LVTS_ATP0(__base) (__base + 0x0070)
> +#define LVTS_ATP1(__base) (__base + 0x0074)
> +#define LVTS_ATP2(__base) (__base + 0x0078)
> +#define LVTS_ATP3(__base) (__base + 0x007C)
> #define LVTS_MSR0(__base) (__base + 0x0090)
> #define LVTS_MSR1(__base) (__base + 0x0094)
> #define LVTS_MSR2(__base) (__base + 0x0098)
> @@ -90,6 +94,7 @@
>
> #define LVTS_MSR_IMMEDIATE_MODE 0
> #define LVTS_MSR_FILTERED_MODE 1
> +#define LVTS_MSR_ATP_MODE 2
Nit: I suggest changing this to an enum since they are related, and
also because these are artificial (unrelated to hardware values).
Otherwise,
Reviewed-by: Chen-Yu Tsai <wenst at chromium.org>
> #define LVTS_MSR_READ_TIMEOUT_US 400
> #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
> @@ -207,6 +212,10 @@ static const struct debugfs_reg32 lvts_regs[] = {
> LVTS_DEBUG_FS_REGS(LVTS_EDATA01),
> LVTS_DEBUG_FS_REGS(LVTS_EDATA02),
> LVTS_DEBUG_FS_REGS(LVTS_EDATA03),
> + LVTS_DEBUG_FS_REGS(LVTS_ATP0),
> + LVTS_DEBUG_FS_REGS(LVTS_ATP1),
> + LVTS_DEBUG_FS_REGS(LVTS_ATP2),
> + LVTS_DEBUG_FS_REGS(LVTS_ATP3),
> LVTS_DEBUG_FS_REGS(LVTS_MSR0),
> LVTS_DEBUG_FS_REGS(LVTS_MSR1),
> LVTS_DEBUG_FS_REGS(LVTS_MSR2),
> @@ -621,6 +630,13 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
> LVTS_IMMD3(lvts_ctrl->base)
> };
>
> + void __iomem *atp_regs[] = {
> + LVTS_ATP0(lvts_ctrl->base),
> + LVTS_ATP1(lvts_ctrl->base),
> + LVTS_ATP2(lvts_ctrl->base),
> + LVTS_ATP3(lvts_ctrl->base)
> + };
> +
> int i;
>
> lvts_for_each_valid_sensor(i, lvts_ctrl_data) {
> @@ -656,8 +672,20 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
> /*
> * Each sensor has its own register address to read from.
> */
> - lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ?
> - imm_regs[i] : msr_regs[i];
> + switch (lvts_ctrl_data->mode) {
> + case LVTS_MSR_IMMEDIATE_MODE:
> + lvts_sensor[i].msr = imm_regs[i];
> + break;
> + case LVTS_MSR_FILTERED_MODE:
> + lvts_sensor[i].msr = msr_regs[i];
> + break;
> + case LVTS_MSR_ATP_MODE:
> + lvts_sensor[i].msr = atp_regs[i];
> + break;
> + default:
> + lvts_sensor[i].msr = imm_regs[i];
> + break;
> + }
>
> lvts_sensor[i].low_thresh = INT_MIN;
> lvts_sensor[i].high_thresh = INT_MIN;
> @@ -907,7 +935,7 @@ static void lvts_ctrl_monitor_enable(struct device *dev, struct lvts_ctrl *lvts_
> u32 sensor_map = 0;
> int i;
>
> - if (lvts_ctrl->mode != LVTS_MSR_FILTERED_MODE)
> + if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE)
> return;
>
> if (enable) {
> --
> 2.39.5
>
>
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