[PATCH v2 06/10] ARM: dts: aspeed-g6: Add PCIe RC node

[Jacky Chou]

Hi Rob,

Thank you for your reply.

> >                                 quality = <100>;
> >                         };
> >
> > +                       pcie_phy1: syscon at 1e6ed200 {
> > +                               compatible = "aspeed,pcie-phy",
> "syscon";
> > +                               reg = <0x1e6ed200 0x100>;
> 
> This looks like part of something else? It should be a child of that.
> 
> If this is the controls for the PCIe PHY, then use the PHY binding instead of your
> own custom phandle property.
> 

Our PCIe design has multiple functions. And the series of patches are submitted for
PCIe RC. The other PCIe functions also use this phy node.
I traced the PHY driver interface, it cannot meet our usage.
Therefore, the RC driver uses the phandle property to configure.
And this syscon also is used by the other PCIe functions.

> > +                       };
> > +
> > +                       pcie_cfg: syscon at 1e770000 {
> > +                               compatible = "aspeed,pcie-cfg",
> "syscon";
> > +                               reg = <0x1e770000 0x80>;
> 
> Looks like this is really part of the PCIe block as a h/w block isn't going to start
> at offset 0xc0.
> 
> 

Actually.
There are two PCIe bus in AST2600
We use the other one PCIe to EP mode, here I call PCIe A.
I call the pcie0 node as PCIe B.
We do not provide PCIe A to RC mode for usage, just EP mode.
But, when PCIe A is used as RC, it reg mapping is starting from 0x1e770080.
I list there mapping.

0x1e77_0000 ~ 0x1e77_007f : common usage
0x1e77_0080 ~ 0x1e77_00bf : PCIE A
0x1e77_00C0 ~ 0x1e77_00ff : PCIE B

So, it is why we create one node to describe common usage for PCIe A and B.
And, why the pcie0 reg mapping is starting from 0x1e77_00c0.

> > +                       };
> > +
> > +                       pcie0: pcie at 1e7700c0 {
> > +                               compatible = "aspeed,ast2600-pcie";
> > +                               device_type = "pci";
> > +                               reg = <0x1e7700c0 0x40>;
> > +                               linux,pci-domain = <0>;
> 
> No need for this. You only have 1 PCI host.
> 

Agreed.
We only provide one RC.

> > +                               #address-cells = <3>;
> > +                               #size-cells = <2>;
> > +                               interrupts = <GIC_SPI 168
> IRQ_TYPE_LEVEL_HIGH>;
> > +                               bus-range = <0x80 0xff>;
> 
> Does this h/w not support bus 0-0x7f for some reason?
> 

List:
PCIE A: 0-0x7f
PCIE B: 0x80-0xff

It is our design on PCIe B to use bus-range 0x80-0xff.

> > +
> > +                               ranges = <0x01000000 0x0
> 0x00018000 0x00018000 0x0 0x00008000
> > +                                         0x02000000 0x0
> 0x70000000
> > + 0x70000000 0x0 0x10000000>;
> > +
> > +                               status = "disabled";
> > +
> > +                               resets = <&syscon
> ASPEED_RESET_H2X>;
> > +                               reset-names = "h2x";
> > +
> > +                               #interrupt-cells = <1>;
> > +                               msi-parent = <&pcie0>;
> > +                               msi-controller;
> > +
> > +                               aspeed,ahbc = <&ahbc>;
> > +                               aspeed,pciecfg = <&pcie_cfg>;
> > +
> > +                               interrupt-map-mask = <0 0 0 7>;
> > +                               interrupt-map = <0 0 0 1 &pcie_intc0
> 0>,
> > +                                               <0 0 0 2
> &pcie_intc0 1>,
> > +                                               <0 0 0 3
> &pcie_intc0 2>,
> > +                                               <0 0 0 4
> &pcie_intc0 3>;
> > +                               pcie_intc0: interrupt-controller {
> > +                                       interrupt-controller;
> > +                                       #address-cells = <0>;
> > +                                       #interrupt-cells = <1>;
> > +                               };
> > +
> > +                               pcie at 8,0 {
> > +                                       reg = <0x804000 0 0 0 0>;
> > +                                       #address-cells = <3>;
> > +                                       #size-cells = <2>;
> > +                                       device_type = "pci";
> > +                                       resets = <&syscon
> ASPEED_RESET_PCIE_RC_O>;
> > +                                       reset-names = "perst";
> > +                                       clocks = <&syscon
> ASPEED_CLK_GATE_BCLK>;
> > +                                       pinctrl-names = "default";
> > +                                       pinctrl-0 =
> <&pinctrl_pcierc1_default>;
> > +                                       aspeed,pciephy =
> <&pcie_phy1>;
> > +                                       ranges;
> > +                               };
> > +                       };
> > +
> >                         gfx: display at 1e6e6000 {
> >                                 compatible = "aspeed,ast2600-gfx",
> "syscon";
> >                                 reg = <0x1e6e6000 0x1000>;
> > --
> > 2.43.0
> >