[boot-wrapper-aarch64 PATCH v2] Enable GCS if it is present in the HW

[Tamas Kaman]

Allow lower level ELs to use GCS when the underlying HW has implmented
the feature. This requires setting SCR_EL3_GCSEn bit in the SCR_EL3
register.

More details of the GCS feature can be found in ARM ARM, chapter 11
https://developer.arm.com/documentation/ddi0487/la/?lang=en

Signed-off-by: Tamas Kaman <tamas.kaman at arm.com>
---
 arch/aarch64/include/asm/cpu.h | 2 ++
 arch/aarch64/init.c            | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index ac50474..91801b0 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -70,6 +70,7 @@
 #define SCR_EL3_ECVEN			BIT(28)
 #define SCR_EL3_TME			BIT(34)
 #define SCR_EL3_HXEn			BIT(38)
+#define SCR_EL3_GCSEn			BIT(39)
 #define SCR_EL3_EnTP2			BIT(41)
 #define SCR_EL3_RCWMASKEn		BIT(42)
 #define SCR_EL3_TCR2EN			BIT(43)
@@ -125,6 +126,7 @@
 #define ID_AA64PFR1_EL1_MTE		BITS(11, 8)
 #define ID_AA64PFR1_EL1_SME		BITS(27, 24)
 #define ID_AA64PFR1_EL1_CSV2_frac	BITS(35, 32)
+#define ID_AA64PFR1_EL1_GCS		BITS(47, 44)
 #define ID_AA64PFR1_EL1_THE		BITS(51, 48)
 
 #define ID_AA64PFR2_EL1			s3_0_c0_c4_2
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index cb24f4e..bb3e835 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -118,6 +118,10 @@ static void cpu_init_el3(void)
 	if (mrs_field(ID_AA64PFR1_EL1, MTE) >= 2)
 		scr |= SCR_EL3_ATA;
 
+	if (mrs_field(ID_AA64PFR1_EL1, GCS)) {
+		scr |= SCR_EL3_GCSEn;
+	}
+
 	if (!kernel_is_32bit())
 		scr |= SCR_EL3_RW;
 
-- 
2.34.1