[PATCH] pwm: mediatek: Fix duty and period setting

[Uwe Kleine-König]

The period generated by the hardware is

	((PWMDWIDTH + 1) << CLKDIV) / freq)

according to my tests with a signal analyser and also the documentation.

The current algorithm doesn't consider the `+ 1` part and so configures
slightly too high periods. The same issue exists for the duty cycle
setting. So subtract 1 from both the register values for period and
duty cycle. If period is 0, bail out, if duty_cycle is 0, just don't set
bit 15 in the CON register.

Note that the handling for duty_cycle == 0 is only based on
experimentation; I don't have access to the documentation and so not
setting bit 15 is just a guess that seems to work in practise.

Fixes: caf065f8fd58 ("pwm: Add MediaTek PWM support")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig at baylibre.com>
---
Hello,

given this problem is more than 8 years old, I won't bother Linus with
this patch before v6.16, but still add a Cc: for stable when committing.
Would be great to get some feedback from people who have access to the
documentation to confirm that the bit 15 handling is sane (or propose a
better alternative).

Best regards
Uwe

 drivers/pwm/pwm-mediatek.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index 6777c511622a..80e322f02512 100644
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -150,7 +150,10 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	do_div(resolution, clk_rate);
 
 	cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
-	while (cnt_period > 8191) {
+	if (!cnt_period)
+		return -EINVAL;
+
+	while (cnt_period > 8192) {
 		resolution *= 2;
 		clkdiv++;
 		cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
@@ -173,9 +176,16 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	}
 
 	cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
-	pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
-	pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
-	pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
+
+	if (cnt_duty) {
+		pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
+		pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period - 1);
+		pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty - 1);
+	} else {
+		pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, clkdiv);
+		pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period - 1);
+		pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, 0);
+	}
 
 out:
 	pwm_mediatek_clk_disable(chip, pwm);

base-commit: a582469541a3f39bed452c50c5d2744620b6db02
-- 
2.49.0