[PATCH RESEND 2/2] arm64: dts: imx95: add jpeg encode and decode nodes

[Frank Li]

On Wed, May 21, 2025 at 01:34:04PM -0400, Frank Li wrote:
> Add jpeg encode\decode and related nodes for i.MX95.

shawn:
	can you help check this?

Frank

>
> Signed-off-by: Frank Li <Frank.Li at nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx95.dtsi | 44 ++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 632631a291122..d38bbe8b16d7e 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -3,6 +3,7 @@
>   * Copyright 2024 NXP
>   */
>
> +#include <dt-bindings/clock/nxp,imx95-clock.h>
>  #include <dt-bindings/dma/fsl-edma.h>
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/input/input.h>
> @@ -1801,6 +1802,49 @@ pcie1_ep: pcie-ep at 4c380000 {
>  			status = "disabled";
>  		};
>
> +		vpu_blk_ctrl: clock-controller at 4c410000 {
> +			compatible = "nxp,imx95-vpu-csr", "syscon";
> +			reg = <0x0 0x4c410000 0x0 0x10000>;
> +			#clock-cells = <1>;
> +			clocks = <&scmi_clk IMX95_CLK_VPUAPB>;
> +			power-domains = <&scmi_devpd IMX95_PD_VPU>;
> +			assigned-clocks = <&scmi_clk IMX95_CLK_VPUAPB>,
> +					  <&scmi_clk IMX95_CLK_VPU>,
> +					  <&scmi_clk IMX95_CLK_VPUJPEG>;
> +			assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>,
> +						 <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>,
> +						 <&scmi_clk IMX95_CLK_SYSPLL1_PFD0>;
> +			assigned-clock-rates = <133333333>, <667000000>, <500000000>;
> +		};
> +
> +		jpegdec: jpegdec at 4c500000 {
> +			compatible = "nxp,imx95-jpgdec", "nxp,imx8qxp-jpgdec";
> +			reg = <0x0 0x4C500000 0x0 0x00050000>;
> +			interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&scmi_clk IMX95_CLK_VPU>,
> +				 <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>;
> +			assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>;
> +			assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>;
> +			power-domains = <&scmi_devpd IMX95_PD_VPU>;
> +		};
> +
> +		jpegenc: jpegenc at 4c550000 {
> +			compatible = "nxp,imx95-jpgenc", "nxp,imx8qxp-jpgenc";
> +			reg = <0x0 0x4C550000 0x0 0x00050000>;
> +			interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&scmi_clk IMX95_CLK_VPU>,
> +				 <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC>;
> +			assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>;
> +			assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>;
> +			power-domains = <&scmi_devpd IMX95_PD_VPU>;
> +		};
> +
>  		netcmix_blk_ctrl: syscon at 4c810000 {
>  			compatible = "nxp,imx95-netcmix-blk-ctrl", "syscon";
>  			reg = <0x0 0x4c810000 0x0 0x8>;
> --
> 2.34.1
>