[PATCH 12/16] pinctrl: samsung: Add ARTPEC-8 SoC specific configuration
ksk4725 at coasia.com
ksk4725 at coasia.com
Wed Jul 9 17:20:42 PDT 2025
From: SeonGu Kang <ksk4725 at coasia.com>
Add Axis ARTPEC-8 SoC specific configuration data to enable pinctrl.
It is similar to other Samsung SoC pinctrl blocks.
Signed-off-by: Priyadarsini G <priya.ganesh at samsung.com>
Signed-off-by: SeonGu Kang <ksk4725 at coasia.com>
---
.../pinctrl/samsung/pinctrl-exynos-arm64.c | 50 +++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-exynos.h | 10 ++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
4 files changed, 63 insertions(+)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index dd07720e32cc..ee3b488b00ff 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -76,6 +76,15 @@ static const struct samsung_pin_bank_type exynos8895_bank_type_off = {
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
};
+/*
+ * Bank type for non-alive type. Bit fields:
+ * CON: 4, DAT: 1, PUD: 4, DRV: 4
+ */
+static const struct samsung_pin_bank_type artpec_bank_type_off = {
+ .fld_width = { 4, 1, 4, 4, },
+ .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
+};
+
/* Pad retention control code for accessing PMU regmap */
static atomic_t exynos_shared_retention_refcnt;
@@ -1814,3 +1823,44 @@ const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
.ctrl = gs101_pin_ctrl,
.num_ctrl = ARRAY_SIZE(gs101_pin_ctrl),
};
+
+/* pin banks of artpec8 pin-controller (FSYS0) */
+static const struct samsung_pin_bank_data artpec8_pin_banks0[] __initconst = {
+ ARTPEC_PIN_BANK_EINTG(5, 0x000, "gpf0", 0x00),
+ ARTPEC_PIN_BANK_EINTG(4, 0x020, "gpf1", 0x04),
+ ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpf2", 0x08),
+ ARTPEC_PIN_BANK_EINTG(4, 0x060, "gpf3", 0x0c),
+ ARTPEC_PIN_BANK_EINTG(7, 0x080, "gpf4", 0x10),
+ ARTPEC_PIN_BANK_EINTG(8, 0x0a0, "gpe0", 0x14),
+ ARTPEC_PIN_BANK_EINTG(8, 0x0c0, "gpe1", 0x18),
+ ARTPEC_PIN_BANK_EINTG(6, 0x0e0, "gpe2", 0x1c),
+ ARTPEC_PIN_BANK_EINTG(8, 0x100, "gps0", 0x20),
+ ARTPEC_PIN_BANK_EINTG(8, 0x120, "gps1", 0x24),
+};
+
+/* pin banks of artpec8 pin-controller (PERIC) */
+static const struct samsung_pin_bank_data artpec8_pin_banks1[] __initconst = {
+ ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
+ ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpa1", 0x04),
+ ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
+ ARTPEC_PIN_BANK_EINTG(2, 0x060, "gpk0", 0x0c),
+};
+
+static const struct samsung_pin_ctrl artpec8_pin_ctrl[] __initconst = {
+ {
+ /* pin-controller instance 0 FSYS data */
+ .pin_banks = artpec8_pin_banks0,
+ .nr_banks = ARRAY_SIZE(artpec8_pin_banks0),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ }, {
+ /* pin-controller instance 1 PERIC data */
+ .pin_banks = artpec8_pin_banks1,
+ .nr_banks = ARRAY_SIZE(artpec8_pin_banks1),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ },
+};
+
+const struct samsung_pinctrl_of_match_data artpec8_of_data __initconst = {
+ .ctrl = artpec8_pin_ctrl,
+ .num_ctrl = ARRAY_SIZE(artpec8_pin_ctrl),
+};
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index b483270ddc53..6bc04cb5ac9f 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -216,6 +216,16 @@
.name = id \
}
+#define ARTPEC_PIN_BANK_EINTG(pins, reg, id, offs) \
+ { \
+ .type = &artpec_bank_type_off, \
+ .pctl_offset = reg, \
+ .nr_pins = pins, \
+ .eint_type = EINT_TYPE_GPIO, \
+ .eint_offset = offs, \
+ .name = id \
+ }
+
/**
* struct exynos_weint_data: irq specific data for all the wakeup interrupts
* generated by the external wakeup interrupt controller.
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 2896eb2de2c0..993efba5a9ad 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1468,6 +1468,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
.data = &s5pv210_of_data },
#endif
#ifdef CONFIG_PINCTRL_EXYNOS_ARM64
+ { .compatible = "axis,artpec8-pinctrl",
+ .data = &artpec8_of_data },
{ .compatible = "google,gs101-pinctrl",
.data = &gs101_of_data },
{ .compatible = "samsung,exynos2200-pinctrl",
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 3cf758df7d69..bfd88ad2f3ff 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -377,6 +377,7 @@ struct samsung_pmx_func {
};
/* list of all exported SoC specific data */
+extern const struct samsung_pinctrl_of_match_data artpec8_of_data;
extern const struct samsung_pinctrl_of_match_data exynos2200_of_data;
extern const struct samsung_pinctrl_of_match_data exynos3250_of_data;
extern const struct samsung_pinctrl_of_match_data exynos4210_of_data;
--
2.34.1
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