[PATCH v7 00/31] Arm GICv5: Host driver implementation

[Marc Zyngier]

On Thu, 03 Jul 2025 11:24:50 +0100,
Lorenzo Pieralisi <lpieralisi at kernel.org> wrote:
> 
> Implement the irqchip kernel driver for the Arm GICv5 architecture,
> as described in the GICv5 beta0 specification, available at:
> 
> https://developer.arm.com/documentation/aes0070
> 
> The GICv5 architecture is composed of multiple components:
> 
> - one or more IRS (Interrupt Routing Service)
> - zero or more ITS (Interrupt Translation Service)
> - zero or more IWB (Interrupt Wire Bridge)
> 
> The GICv5 host kernel driver is organized into units corresponding
> to GICv5 components.
> 
> The GICv5 architecture defines the following interrupt types:
> 
> - PPI (PE-Private Peripheral Interrupt)
> - SPI (Shared Peripheral Interrupt)
> - LPI (Logical Peripheral Interrupt)
> 
> This series adds sysreg entries required to automatically generate
> GICv5 registers handling code, one patch per-register.
> 
> This patch series is split into patches matching *logical* entities,
> to make the review easier.

[...]

Oliver, I've pushed out a branch with these patches at [1]. Could you
please stash it in kvmarm/next and add the KVM bits to it so that it
can all simmer in -next for a bit?

Thanks,

	M.

[1] git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git gic-v5-host

-- 
Without deviation from the norm, progress is not possible.