[PATCH 3/3] PCI: brcmstb: Enable Broadcom Cable Modem SoCs

[Manivannan Sadhasivam]

On Mon, Jun 09, 2025 at 06:17:06PM GMT, Jim Quinlan wrote:
> Broadcom's Cable Modem (CM) group also uses this PCIe driver
> as it shares the PCIe HW core with the STB group.
> 
> Make the modifications to enable the CM SoCs.
> 
> Signed-off-by: Jim Quinlan <james.quinlan at broadcom.com>
> ---
>  drivers/pci/controller/pcie-brcmstb.c | 186 +++++++++++++++++++++-----
>  1 file changed, 152 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index db7872cda960..e25dbcdc56a7 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -51,6 +51,9 @@
>  #define PCIE_RC_CFG_PRIV1_ROOT_CAP			0x4f8
>  #define  PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK	0xf8
>  
> +#define PCIE_RC_DL_PDL_CONTROL_4			0x1010
> +#define  PCIE_RC_DL_PDL_CONTROL_4_NPH_FC_INIT_MASK	0xff000000
> +
>  #define PCIE_RC_DL_MDIO_ADDR				0x1100
>  #define PCIE_RC_DL_MDIO_WR_DATA				0x1104
>  #define PCIE_RC_DL_MDIO_RD_DATA				0x1108
> @@ -60,6 +63,7 @@
>  #define  PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK	0xff
>  
>  #define PCIE_MISC_MISC_CTRL				0x4008
> +#define  PCIE_MISC_MISC_CTRL_PCIE_IN_CPL_RO_MASK	0x20
>  #define  PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK	0x80
>  #define  PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK	0x400
>  #define  PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK		0x1000
> @@ -170,6 +174,7 @@
>  /* MSI target addresses */
>  #define BRCM_MSI_TARGET_ADDR_LT_4GB	0x0fffffffcULL
>  #define BRCM_MSI_TARGET_ADDR_GT_4GB	0xffffffffcULL
> +#define BRCM_MSI_TARGET_ADDR_FOR_CM	0xfffffffffcULL
>  
>  /* MDIO registers */
>  #define MDIO_PORT0			0x0
> @@ -223,13 +228,23 @@ enum {
>  enum pcie_soc_base {
>  	GENERIC,
>  	BCM2711,
> +	BCM3162,
> +	BCM3392,
> +	BCM3390,
>  	BCM4908,
>  	BCM7278,
>  	BCM7425,
>  	BCM7435,
>  	BCM7712,
> +	BCM33940,
>  };
>  
> +/*
> + * BCM3390 CM chip actually conforms to STB design, so it
> + * is not present in the macro below.
> + */
> +#define IS_CM_SOC(t) ((t) == BCM3162 || (t) == BCM33940 || (t) == BCM3392)
> +
>  struct inbound_win {
>  	u64 size;
>  	u64 pci_offset;
> @@ -757,6 +772,9 @@ static int brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
>  	u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT;
>  	int ret = 0;
>  
> +	if (IS_CM_SOC(pcie->cfg->soc_base))
> +		return 0;
> +
>  	if (pcie->bridge_reset) {
>  		if (val)
>  			ret = reset_control_assert(pcie->bridge_reset);
> @@ -891,13 +909,13 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie,
>  	struct inbound_win *b = b_begin;
>  
>  	/*
> -	 * STB chips beside 7712 disable the first inbound window default.
> -	 * Rather being mapped to system memory it is mapped to the
> -	 * internal registers of the SoC.  This feature is deprecated, has
> -	 * security considerations, and is not implemented in our modern
> -	 * SoCs.
> +	 * STB chips beside CM chips and 7712 disable the first inbound
> +	 * window default.  Rather being mapped to system memory it is
> +	 * mapped to the internal registers of the SoC.  This feature is
> +	 * deprecated, has security considerations, and is not
> +	 * implemented in our modern SoCs.

May I know what is the purpose of allowing inbound access to these regions? TBH,
I'm not sure what is the usecase of 'inbound memory' for PCIe host.

- Mani

-- 
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