[PATCH v2 4/4] arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support

[Andre Przywara]

On Mon,  7 Jul 2025 18:51:55 +0200
Paul Kocialkowski <paulk at sys-base.io> wrote:

Hi Paul,

> The Liontron H-A133L board features an Ethernet controller with a
> JLSemi JL1101 PHY. Its reset pin is tied to the PH12 GPIO.
> 
> Note that the reset pin must be handled as a bus-wide reset GPIO in
> order to let the MDIO core properly reset it before trying to read
> its identification registers. There's no other device on the MDIO bus.

putting the PHY reset GPIO into the MDIO node is a clever solution, I
was struggling with putting it either in the MAC or PHY node, though
conceptually it would still belong in the latter, I think. But this
might be a more generic problem: for most other devices we activate
reset and clock gates *before* trying to access them, though this might
be historically different for Ethernet PHYs.
 
> The datasheet of the PHY mentions that the reset signal must be held
> for 1 ms to take effect. Make it 2 ms (and the same for post-delay) to
> be on the safe side without wasting too much time during boot.
> 
> Signed-off-by: Paul Kocialkowski <paulk at sys-base.io>

Despite the above, this looks fine, and works for me:

Reviewed-by: Andre Przywara <andre.przywara at arm.com>
Tested-by: Andre Przywara <andre.przywara at arm.com>

Cheers,
Andre

> ---
>  .../sun50i-a133-liontron-h-a133l.dts          | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts b/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts
> index fe77178d3e33..90a50910f07b 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts
> @@ -65,6 +65,25 @@ &ehci1 {
>  	status = "okay";
>  };
>  
> +&emac0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&rmii0_pins>;
> +	phy-handle = <&rmii_phy>;
> +	phy-mode = "rmii";
> +	status = "okay";
> +};
> +
> +&mdio0 {
> +	reset-gpios = <&pio 7 12 GPIO_ACTIVE_LOW>; /* PH12 */
> +	reset-delay-us = <2000>;
> +	reset-post-delay-us = <2000>;
> +
> +	rmii_phy: ethernet-phy at 1 {
> +		compatible = "ethernet-phy-ieee802.3-c22";
> +		reg = <1>;
> +	};
> +};
> +
>  &mmc0 {
>  	vmmc-supply = <&reg_dcdc1>;
>  	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */