[PATCH v3 07/22] perf: arm_pmuv3: Generalize counter bitmasks

[Mark Rutland]

On Thu, Jun 26, 2025 at 08:04:43PM +0000, Colton Lewis wrote:
> The OVSR bitmasks are valid for enable and interrupt registers as well as
> overflow registers. Generalize the names.
> 
> Signed-off-by: Colton Lewis <coltonlewis at google.com>

FWIW, this looks fine to me, so:

Acked-by: Mark Rutland <mark.rutland at arm.com>

Mark.

> ---
>  drivers/perf/arm_pmuv3.c       |  4 ++--
>  include/linux/perf/arm_pmuv3.h | 14 +++++++-------
>  2 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c
> index 6358de6c9fab..3bc016afea34 100644
> --- a/drivers/perf/arm_pmuv3.c
> +++ b/drivers/perf/arm_pmuv3.c
> @@ -513,7 +513,7 @@ static u64 armv8pmu_pmcr_n_read(void)
>  
>  static int armv8pmu_has_overflowed(u64 pmovsr)
>  {
> -	return !!(pmovsr & ARMV8_PMU_OVERFLOWED_MASK);
> +	return !!(pmovsr & ARMV8_PMU_CNT_MASK_ALL);
>  }
>  
>  static int armv8pmu_counter_has_overflowed(u64 pmnc, int idx)
> @@ -749,7 +749,7 @@ static u64 armv8pmu_getreset_flags(void)
>  	value = read_pmovsclr();
>  
>  	/* Write to clear flags */
> -	value &= ARMV8_PMU_OVERFLOWED_MASK;
> +	value &= ARMV8_PMU_CNT_MASK_ALL;
>  	write_pmovsclr(value);
>  
>  	return value;
> diff --git a/include/linux/perf/arm_pmuv3.h b/include/linux/perf/arm_pmuv3.h
> index d698efba28a2..fd2a34b4a64d 100644
> --- a/include/linux/perf/arm_pmuv3.h
> +++ b/include/linux/perf/arm_pmuv3.h
> @@ -224,14 +224,14 @@
>  				 ARMV8_PMU_PMCR_LC | ARMV8_PMU_PMCR_LP)
>  
>  /*
> - * PMOVSR: counters overflow flag status reg
> + * Counter bitmask layouts for overflow, enable, and interrupts
>   */
> -#define ARMV8_PMU_OVSR_P		GENMASK(30, 0)
> -#define ARMV8_PMU_OVSR_C		BIT(31)
> -#define ARMV8_PMU_OVSR_F		BIT_ULL(32) /* arm64 only */
> -/* Mask for writable bits is both P and C fields */
> -#define ARMV8_PMU_OVERFLOWED_MASK	(ARMV8_PMU_OVSR_P | ARMV8_PMU_OVSR_C | \
> -					ARMV8_PMU_OVSR_F)
> +#define ARMV8_PMU_CNT_MASK_P		GENMASK(30, 0)
> +#define ARMV8_PMU_CNT_MASK_C		BIT(31)
> +#define ARMV8_PMU_CNT_MASK_F		BIT_ULL(32) /* arm64 only */
> +#define ARMV8_PMU_CNT_MASK_ALL		(ARMV8_PMU_CNT_MASK_P | \
> +					 ARMV8_PMU_CNT_MASK_C | \
> +					 ARMV8_PMU_CNT_MASK_F)
>  
>  /*
>   * PMXEVTYPER: Event selection reg
> -- 
> 2.50.0.727.gbf7dc18ff4-goog
>