[PATCH 1/2] clk: sunxi-ng: v3s: Fix de clock definition

[Icenowy Zheng]

在 2025-07-04星期五的 23:52 +0200，Paul Kocialkowski写道：
> Hi,
> 
> Le Fri 04 Jul 25, 23:54, Icenowy Zheng a écrit :
> > 在 2025-07-04星期五的 17:40 +0200，Paul Kocialkowski写道：
> > > The de clock is marked with CLK_SET_RATE_PARENT, which is really
> > > not
> > > necessary (as confirmed from experimentation) and significantly
> > > restricts flexibility for other clocks using the same parent.
> > 
> > With it not setting parent, is arbitary pixel clocks still
> > possible?
> 
> Absolutely and the clock tree is very much improved, I think the flag
> was the
> reason that was preventing it from naturally keeping the tcon and de
> clocks
> under the video pll in my case.
> 
> Now it can provide both the 33 Mhz for the pixel clock and runs the
> mixer at
> nearly 150 MHz. The video pll now runs at 297 MHz which is a perfect

Did you test other pixel clocks?

I suggest you to try a RGB-to-VGA bridge and test possible pixel clocks
on the VGA port.

> fit for
> csi-sclk camera main clock, so the algorithm is doing its job at its
> best!
> 
> So this means that I no longer have to change the mixer clock to 297
> MHz to
> keep it under the video pll. It pretty much solves all my problems at
> once.
> 
> Here is the relevant clk_summary extract:
>     pll-video                        2       2        2       
> 297000000   50000      0     50000      Y     
> deviceless                      no_connection_id         
>        csi-sclk                      0       0        3       
> 297000000   50000      0     50000      N        
> 1cb8000.isp                     mod                      
>                                                                      
>                                            
> 1cb0000.camera                  mod                      
>                                                                      
>                                            
> 1cb1000.csi                     mod                      
>        tcon                          2       2        1       
> 33000000    50000      0     50000      Y         1c0c000.lcd-
> controller          tcon-ch0                 
>           tcon-data-clock            1       1        1       
> 33000000    50000      0     50000      Y           
> deviceless                      no_connection_id         
>        de                            2       2        0       
> 297000000   50000      0     50000      Y        
> 1000000.clock                   mod                      
>           wb-div                     0       0        0       
> 297000000   50000      0     50000      Y           
> deviceless                      no_connection_id         
>              wb                      0       0        0       
> 297000000   50000      0     50000      N              
> deviceless                      no_connection_id         
>           mixer0-div                 1       1        0       
> 148500000   50000      0     50000      Y           
> deviceless                      no_connection_id         
>              mixer0                  1       1        0       
> 148500000   50000      0     50000      Y              
> 1100000.mixer                   mod                      
> 
> Cheers,
> 
> Paul
> 
> > > 
> > > In addition the source selection (parent) field is marked as
> > > using
> > > 2 bits, when it the documentation reports that it uses 3.
> > > 
> > > Fix both issues in the de clock definition.
> > > 
> > > Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
> > > Signed-off-by: Paul Kocialkowski <paulk at sys-base.io>
> > > ---
> > >  drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +--
> > >  1 file changed, 1 insertion(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> > > b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> > > index 52e4369664c5..df345a620d8d 100644
> > > --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> > > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> > > @@ -347,8 +347,7 @@ static
> > > SUNXI_CCU_GATE(dram_ohci_clk,        "dram-ohci",    "dram",
> > >  
> > >  static const char * const de_parents[] = { "pll-video", "pll-
> > > periph0" };
> > >  static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
> > > -                                0x104, 0, 4, 24, 2, BIT(31),
> > > -                                CLK_SET_RATE_PARENT);
> > > +                                0x104, 0, 4, 24, 3, BIT(31), 0);
> > >  
> > >  static const char * const tcon_parents[] = { "pll-video", "pll-
> > > periph0" };
> > >  static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
> > 
>