[PATCH 1/2] clk: sunxi-ng: v3s: Fix de clock definition

[Icenowy Zheng]

在 2025-07-04星期五的 17:40 +0200，Paul Kocialkowski写道：
> The de clock is marked with CLK_SET_RATE_PARENT, which is really not
> necessary (as confirmed from experimentation) and significantly
> restricts flexibility for other clocks using the same parent.

With it not setting parent, is arbitary pixel clocks still possible?

> 
> In addition the source selection (parent) field is marked as using
> 2 bits, when it the documentation reports that it uses 3.
> 
> Fix both issues in the de clock definition.
> 
> Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
> Signed-off-by: Paul Kocialkowski <paulk at sys-base.io>
> ---
>  drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> index 52e4369664c5..df345a620d8d 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> @@ -347,8 +347,7 @@ static
> SUNXI_CCU_GATE(dram_ohci_clk,        "dram-ohci",    "dram",
>  
>  static const char * const de_parents[] = { "pll-video", "pll-
> periph0" };
>  static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
> -                                0x104, 0, 4, 24, 2, BIT(31),
> -                                CLK_SET_RATE_PARENT);
> +                                0x104, 0, 4, 24, 3, BIT(31), 0);
>  
>  static const char * const tcon_parents[] = { "pll-video", "pll-
> periph0" };
>  static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,