[PATCH v7 15/31] arm64: Disable GICv5 read/write/instruction traps

[Catalin Marinas]

On Thu, Jul 03, 2025 at 12:25:05PM +0200, Lorenzo Pieralisi wrote:
> GICv5 trap configuration registers value is UNKNOWN at reset.
> 
> Initialize GICv5 EL2 trap configuration registers to prevent
> trapping GICv5 instruction/register access upon entering the
> kernel.
> 
> Signed-off-by: Lorenzo Pieralisi <lpieralisi at kernel.org>
> Reviewed-by: Marc Zyngier <maz at kernel.org>
> Cc: Will Deacon <will at kernel.org>
> Cc: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Marc Zyngier <maz at kernel.org>

Acked-by: Catalin Marinas <catalin.marinas at arm.com>