[PATCH v2 1/5] irqchip/gic-v5: Skip deactivate for forwarded PPI interrupts

Sascha Bischoff Sascha.Bischoff at arm.com
Thu Jul 3 01:58:02 PDT 2025


On Wed, 2025-07-02 at 15:28 +0100, Jonathan Cameron wrote:
> On Fri, 27 Jun 2025 10:09:01 +0000
> Sascha Bischoff <Sascha.Bischoff at arm.com> wrote:
> 
> > If a PPI interrupt is forwarded to a guest, skip the deactivate and
> > only EOI. Rely on the guest deactivating both the virtual and
> > physical
> > interrupts (due to ICH_LRx_EL2.HW being set) later on as part of
> > handling the injected interrupt. This mimics the behaviour seen on
> > native GICv3.
> > 
> > This is part of adding support for the GICv3 compatibility mode on
> > a
> > GICv5 host.
> > 
> > Reviewed-by: Lorenzo Pieralisi <lpieralisi at kernel.org>
> > 
> 
> Trivial but no gaps in tag blocks.  So no blank line here.
> Some scripting will moan about this and I think that will hit you if
> this goes into linux next.

Ah, thanks for pointing that out! I've fixed that (and tag ordering -
thanks, Lorenzo).

Thanks,
Sascha

> 
> > Co-authored-by: Timothy Hayes <timothy.hayes at arm.com>
> > Signed-off-by: Timothy Hayes <timothy.hayes at arm.com>
> > Signed-off-by: Sascha Bischoff <sascha.bischoff at arm.com>
> > ---
> >  drivers/irqchip/irq-gic-v5.c | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> > 
> > diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-
> > gic-v5.c
> > index 7a11521eeeca..6b42c4af5c79 100644
> > --- a/drivers/irqchip/irq-gic-v5.c
> > +++ b/drivers/irqchip/irq-gic-v5.c
> > @@ -213,6 +213,12 @@ static void gicv5_hwirq_eoi(u32 hwirq_id, u8
> > hwirq_type)
> >  
> >  static void gicv5_ppi_irq_eoi(struct irq_data *d)
> >  {
> > +	/* Skip deactivate for forwarded PPI interrupts */
> > +	if (irqd_is_forwarded_to_vcpu(d)) {
> > +		gic_insn(0, CDEOI);
> > +		return;
> > +	}
> > +
> >  	gicv5_hwirq_eoi(d->hwirq, GICV5_HWIRQ_TYPE_PPI);
> >  }
> >  
> > @@ -494,6 +500,16 @@ static bool
> > gicv5_ppi_irq_is_level(irq_hw_number_t hwirq)
> >  	return !!(read_ppi_sysreg_s(hwirq, PPI_HM) & bit);
> >  }
> >  
> > +static int gicv5_ppi_irq_set_vcpu_affinity(struct irq_data *d,
> > void *vcpu)
> > +{
> > +	if (vcpu)
> > +		irqd_set_forwarded_to_vcpu(d);
> > +	else
> > +		irqd_clr_forwarded_to_vcpu(d);
> > +
> > +	return 0;
> > +}
> > +
> >  static const struct irq_chip gicv5_ppi_irq_chip = {
> >  	.name			= "GICv5-PPI",
> >  	.irq_mask		= gicv5_ppi_irq_mask,
> > @@ -501,6 +517,7 @@ static const struct irq_chip gicv5_ppi_irq_chip
> > = {
> >  	.irq_eoi		= gicv5_ppi_irq_eoi,
> >  	.irq_get_irqchip_state	= gicv5_ppi_irq_get_irqchip_state,
> >  	.irq_set_irqchip_state	= gicv5_ppi_irq_set_irqchip_state,
> > +	.irq_set_vcpu_affinity	= gicv5_ppi_irq_set_vcpu_affinity,
> >  	.flags			= IRQCHIP_SKIP_SET_WAKE	 
> > |
> >  				  IRQCHIP_MASK_ON_SUSPEND,
> >  };
> 



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