[PATCH 5/5] arm64: dts: imx943: Add LVDS/DISPLAY CSR nodes

[Peng Fan]

On Tue, Jul 01, 2025 at 11:28:07AM +0200, Alexander Stein wrote:
>Hi,
>
>Am Dienstag, 1. Juli 2025, 09:04:41 CEST schrieb Peng Fan:
>> Add nodes for LVDS/DISPLAY CSR.
>> 
>> Add ldb_pll_div7 node which is used for clock source of DISPLAY CSR.
>> 
>> Signed-off-by: Peng Fan <peng.fan at nxp.com>
>> ---
>>  arch/arm64/boot/dts/freescale/imx943.dtsi | 34 +++++++++++++++++++++++++++++++
>>  1 file changed, 34 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
>> index 45b8da758e87771c0775eb799ce2da3aac37c060..cf67dba21e4f6f27fff7e5d29744086e4ec9c021 100644
>> --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
>
>Why is this specific to imx943 but not imx94? What is the difference anyway?

There is only i.MX943 in i.MX94 family as of now. Other future variants
may not support lvds or display. So Add the nodes in imx943.dtsi.

In future if the family has more and more members, and they
lvds and display supported, we could move back to imx94.dtsi.

No specific reason.

Thanks
Peng

>
>Best regards
>Alexander
>
>> @@ -3,6 +3,8 @@
>>   * Copyright 2025 NXP
>>   */
>>  
>> +#include <dt-bindings/clock/nxp,imx94-clock.h>
>> +
>>  #include "imx94.dtsi"
>>  
>>  / {
>> @@ -145,4 +147,36 @@ l3_cache: l3-cache {
>>  			cache-unified;
>>  		};
>>  	};
>> +
>> +	ldb_pll_pixel: ldb_pll_div7 {
>> +		compatible = "fixed-factor-clock";
>> +		#clock-cells = <0>;
>> +		clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
>> +		clock-div = <7>;
>> +		clock-mult = <1>;
>> +		clock-output-names = "ldb_pll_div7";
>> +	};
>> +
>> +	soc {
>> +		dispmix_csr: syscon at 4b010000 {
>> +			compatible = "nxp,imx94-display-csr", "syscon";
>> +			reg = <0x0 0x4b010000 0x0 0x10000>;
>> +			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
>> +			#clock-cells = <1>;
>> +			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
>> +			assigned-clocks = <&scmi_clk IMX94_CLK_DISPAXI>,
>> +					  <&scmi_clk IMX94_CLK_DISPAPB>;
>> +			assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>,
>> +						 <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
>> +			assigned-clock-rates = <400000000>,  <133333333>;
>> +		};
>> +
>> +		lvds_csr: syscon at 4b0c0000 {
>> +			compatible = "nxp,imx94-lvds-csr", "syscon";
>> +			reg = <0x0 0x4b0c0000 0x0 0x10000>;
>> +			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
>> +			#clock-cells = <1>;
>> +			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
>> +		};
>> +	};
>>  };
>> 
>> 
>
>
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