[RESEND PATCH] ARM: dts: socfpga: Add basic support for Terrasic's de10-nano

[Krzysztof Kozlowski]

On 28/01/2025 18:29, Uwe Kleine-König wrote:
> This dts is enough to make the board boot to Linux with the rootfs on
> a micro SD card.
> 
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig at baylibre.com>
> ---
> Hello,
> 
> in the variant I sent 15 min ago I fatfingered the address of the
> linux-arm-kernel list. So here comes a resend with the right address ...
> 
> Sorry for the noise
> Uwe
> 
>  arch/arm/boot/dts/intel/socfpga/Makefile      |  1 +
>  .../socfpga/socfpga_cyclone5_de10nano.dts     | 90 +++++++++++++++++++
>  2 files changed, 91 insertions(+)
>  create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts
> 
> diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile
> index c467828aeb4b..7f69a0355ea5 100644
> --- a/arch/arm/boot/dts/intel/socfpga/Makefile
> +++ b/arch/arm/boot/dts/intel/socfpga/Makefile
> @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
>  	socfpga_cyclone5_mcvevk.dtb \
>  	socfpga_cyclone5_socdk.dtb \
>  	socfpga_cyclone5_de0_nano_soc.dtb \
> +	socfpga_cyclone5_de10nano.dtb \
>  	socfpga_cyclone5_sockit.dtb \
>  	socfpga_cyclone5_socrates.dtb \
>  	socfpga_cyclone5_sodia.dtb \
> diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts
> new file mode 100644
> index 000000000000..d1f23a57a94d
> --- /dev/null
> +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts
> @@ -0,0 +1,90 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2017, Intel Corporation
> + *
> + * based on socfpga_cyclone5_de0_nano_soc.dts
> + */
> +/dts-v1/;
> +
> +#include "socfpga_cyclone5.dtsi"
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> +	model = "Terasic DE10-Nano";
> +	compatible = "altr,socfpga-cyclone5", "altr,socfpga";

Incorrect compatible. It's not cyclone5 board. cyclone5 is the SoC.

There is no altr,socfpga

This wasn't ever tested with bindings.


> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory at 0 {
> +		/* 1 GiB */
> +		device_type = "memory";
> +		reg = <0x0 0x40000000>;
> +	};
> +
> +	soc {
> +		fpga_axi: axi_h2f_lw_bridge at ff200000 {

Follow DTS coding style. You just sent us something from downstream.

> +			compatible = "simple-bus";
> +			reg = <0xff200000 0x00200000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;

ranges would be after reg, but they are pointless here, no? Where is the
child?

> +			ranges = <0x00000000 0xff200000 0x00200000>;
> +		};
> +	};
> +};
> +
> +&gmac1 {
> +	/* Uses a KSZ9031RNX phy */
> +	status = "okay";
> +	phy-mode = "rgmii";
> +
> +	rxd0-skew-ps = <420>;
> +	rxd1-skew-ps = <420>;
> +	rxd2-skew-ps = <420>;
> +	rxd3-skew-ps = <420>;
> +	txen-skew-ps = <0>;
> +	txc-skew-ps = <1860>;
> +	rxdv-skew-ps = <420>;
> +	rxc-skew-ps = <1680>;
> +};
> +
> +&gpio0 {
> +	status = "okay";
> +};
> +
> +&gpio1 {
> +	status = "okay";
> +};
> +
> +&gpio2 {
> +	status = "okay";
> +};
> +
> +&i2c0 {
> +	clock-frequency = <100000>;
> +	status = "okay";
> +
> +	accelerometer at 53 {
> +		compatible = "adi,adxl34x";

There is no such compatible and nothing in changelog refers to missing
bindings. Always provide link in the changelog to your bindings which
were not yet accepted.


Best regards,
Krzysztof