[PATCH] dt-bindings: soc: Add new board description for Versal NET
Michal Simek
michal.simek at amd.com
Mon Jan 20 23:51:36 PST 2025
On 1/10/25 17:00, Rob Herring wrote:
> On Wed, Jan 08, 2025 at 05:03:38PM +0530, Shubhrajyoti Datta wrote:
>> The Versal NET (Networked Adaptive Compute Acceleration Platform) from
>> AMD/Xilinx is a next-generation adaptive platform designed for high
>> performance computing, networking, and AI acceleration. It is part of the
>> Versal ACAP (Adaptive Compute Acceleration Platform) family.
>>
>> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta at amd.com>
>> ---
>>
>> Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 6 +++++-
>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
>> index 131aba5ed9f4..e0fa36be7e35 100644
>> --- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
>> +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
>> @@ -10,7 +10,7 @@ maintainers:
>> - Michal Simek <michal.simek at amd.com>
>>
>> description: |
>> - Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
>> + Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC or Versal Adaptive SoCs
>
> Perhaps make this more general instead of adding to it for each SoC.
>
> Also, the '|' can be dropped while you are here.
It should be likely AMD/Xilinx SOCs
>
>>
>> properties:
>> $nodename:
>> @@ -187,6 +187,10 @@ properties:
>> - const: qemu,mbv
>> - const: amd,mbv
>>
>> + - description: Xilinx Versal NET
>
> Above you say "Versal Adaptive", but not here?
Family is marked as Versal Adaptive SOCs which contains couple of products.
Versal, Versal NET or Versal Gen 2.
Thanks,
Michal
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