[PATCH v3 6/6] PCI: dw-rockchip: Describe resizable BARs as resizable BARs

[Manivannan Sadhasivam]

On Mon, Jan 13, 2025 at 11:27:37AM +0100, Niklas Cassel wrote:
> Looking at "11.4.4.29 USP_PCIE_RESBAR Registers Summary" in the rk3588 TRM,
> we can see that none of the BARs are Fixed BARs, but actually Resizable
> BARs.
> 
> I couldn't find any reference in the rk3568 TRM, but looking at the
> downstream PCIe endpoint driver, rk3568 and rk3588 are treated as the same,
> so the BARs on rk3568 must also be Resizable BARs.
> 
> Now when we actually have support for Resizable BARs, let's configure
> these BARs as such.
> 
> Signed-off-by: Niklas Cassel <cassel at kernel.org>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org>

- Mani

> ---
>  drivers/pci/controller/dwc/pcie-dw-rockchip.c | 22 +++++++++----------
>  1 file changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index ce4b511bff9b..6a307a961756 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -273,12 +273,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = {
>  	.msi_capable = true,
>  	.msix_capable = true,
>  	.align = SZ_64K,
> -	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> -	.bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> -	.bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> -	.bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> -	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> -	.bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> +	.bar[BAR_0] = { .type = BAR_RESIZABLE, },
> +	.bar[BAR_1] = { .type = BAR_RESIZABLE, },
> +	.bar[BAR_2] = { .type = BAR_RESIZABLE, },
> +	.bar[BAR_3] = { .type = BAR_RESIZABLE, },
> +	.bar[BAR_4] = { .type = BAR_RESIZABLE, },
> +	.bar[BAR_5] = { .type = BAR_RESIZABLE, },
>  };
>  
>  /*
> @@ -293,12 +293,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = {
>  	.msi_capable = true,
>  	.msix_capable = true,
>  	.align = SZ_64K,
> -	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> -	.bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> -	.bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> -	.bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> +	.bar[BAR_0] = { .type = BAR_RESIZABLE, },
> +	.bar[BAR_1] = { .type = BAR_RESIZABLE, },
> +	.bar[BAR_2] = { .type = BAR_RESIZABLE, },
> +	.bar[BAR_3] = { .type = BAR_RESIZABLE, },
>  	.bar[BAR_4] = { .type = BAR_RESERVED, },
> -	.bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> +	.bar[BAR_5] = { .type = BAR_RESIZABLE, },
>  };
>  
>  static const struct pci_epc_features *
> -- 
> 2.47.1
> 

-- 
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