[PATCH 2/5] arm64: dts: renesas: spider-ethernet: Access rswitch ports via phandles

[Marek Vasut]

The r8a779f0.dtsi now contains labels for each rswitch port in
the form 'rswitchportN'. Use those to access rswitch ports and
slightly reduce the depth of this board DT. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
---
Cc: Conor Dooley <conor+dt at kernel.org>
Cc: Geert Uytterhoeven <geert+renesas at glider.be>
Cc: Krzysztof Kozlowski <krzk+dt at kernel.org>
Cc: Rob Herring <robh at kernel.org>
Cc: devicetree at vger.kernel.org
Cc: linux-renesas-soc at vger.kernel.org
---
 .../dts/renesas/r8a779f0-spider-ethernet.dtsi | 87 +++++++++----------
 1 file changed, 42 insertions(+), 45 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
index 5d38669ed1ec3..069f36ba53a4f 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
@@ -42,61 +42,58 @@ &rswitch {
 	pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>;
 	pinctrl-names = "default";
 	status = "okay";
+};
+
+&rswitchport0 {
+	reg = <0>;
+	phy-handle = <&u101>;
+	phy-mode = "sgmii";
+	phys = <&eth_serdes 0>;
 
-	ethernet-ports {
+	mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		port at 0 {
-			reg = <0>;
-			phy-handle = <&u101>;
-			phy-mode = "sgmii";
-			phys = <&eth_serdes 0>;
-
-			mdio {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				u101: ethernet-phy at 1 {
-					reg = <1>;
-					compatible = "ethernet-phy-ieee802.3-c45";
-					interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>;
-				};
-			};
-		};
-		port at 1 {
+		u101: ethernet-phy at 1 {
 			reg = <1>;
-			phy-handle = <&u201>;
-			phy-mode = "sgmii";
-			phys = <&eth_serdes 1>;
+			compatible = "ethernet-phy-ieee802.3-c45";
+			interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
 
-			mdio {
-				#address-cells = <1>;
-				#size-cells = <0>;
+&rswitchport1 {
+	reg = <1>;
+	phy-handle = <&u201>;
+	phy-mode = "sgmii";
+	phys = <&eth_serdes 1>;
 
-				u201: ethernet-phy at 2 {
-					reg = <2>;
-					compatible = "ethernet-phy-ieee802.3-c45";
-					interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>;
-				};
-			};
-		};
-		port at 2 {
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		u201: ethernet-phy at 2 {
 			reg = <2>;
-			phy-handle = <&u301>;
-			phy-mode = "sgmii";
-			phys = <&eth_serdes 2>;
+			compatible = "ethernet-phy-ieee802.3-c45";
+			interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
+
+&rswitchport2 {
+	reg = <2>;
+	phy-handle = <&u301>;
+	phy-mode = "sgmii";
+	phys = <&eth_serdes 2>;
 
-			mdio {
-				#address-cells = <1>;
-				#size-cells = <0>;
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
 
-				u301: ethernet-phy at 3 {
-					reg = <3>;
-					compatible = "ethernet-phy-ieee802.3-c45";
-					interrupts-extended = <&gpio3 9 IRQ_TYPE_LEVEL_LOW>;
-				};
-			};
+		u301: ethernet-phy at 3 {
+			reg = <3>;
+			compatible = "ethernet-phy-ieee802.3-c45";
+			interrupts-extended = <&gpio3 9 IRQ_TYPE_LEVEL_LOW>;
 		};
 	};
 };
-- 
2.45.2