[PATCH net-next v3 5/6] net: xilinx: axienet: Get coalesce parameters from driver state

[Simon Horman]

On Fri, Jan 10, 2025 at 02:26:15PM -0500, Sean Anderson wrote:
> The cr variables now contain the same values as the control registers
> themselves. Extract/calculate the values from the variables instead of
> saving the user-specified values. This allows us to remove some
> bookeeping, and also lets the user know what the actual coalesce
> settings are.
> 
> Signed-off-by: Sean Anderson <sean.anderson at linux.dev>
> Reviewed by: Shannon Nelson <shannon.nelson at amd.com>

Hi Sean,

Unfortunately this series does not appear to apply cleanly to net-next.
Which is our CI is currently unable to cope with :(

Please consider rebasing and reposting.

> ---
> 
> (no changes since v2)
> 
> Changes in v2:
> - New
> 
>  drivers/net/ethernet/xilinx/xilinx_axienet.h  |  8 ---
>  .../net/ethernet/xilinx/xilinx_axienet_main.c | 70 +++++++++++++------
>  2 files changed, 47 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
> index 6b8e550c2155..45d8d80dbb1a 100644
> --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
> @@ -533,10 +533,6 @@ struct skbuf_dma_descriptor {
>   *		  supported, the maximum frame size would be 9k. Else it is
>   *		  1522 bytes (assuming support for basic VLAN)
>   * @rxmem:	Stores rx memory size for jumbo frame handling.
> - * @coalesce_count_rx:	Store the irq coalesce on RX side.
> - * @coalesce_usec_rx:	IRQ coalesce delay for RX
> - * @coalesce_count_tx:	Store the irq coalesce on TX side.
> - * @coalesce_usec_tx:	IRQ coalesce delay for TX
>   * @use_dmaengine: flag to check dmaengine framework usage.
>   * @tx_chan:	TX DMA channel.
>   * @rx_chan:	RX DMA channel.
> @@ -615,10 +611,6 @@ struct axienet_local {
>  	u32 max_frm_size;
>  	u32 rxmem;
>  
> -	u32 coalesce_count_rx;
> -	u32 coalesce_usec_rx;
> -	u32 coalesce_count_tx;
> -	u32 coalesce_usec_tx;
>  	u8  use_dmaengine;
>  	struct dma_chan *tx_chan;
>  	struct dma_chan *rx_chan;

> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c

...

> @@ -260,6 +264,23 @@ static u32 axienet_calc_cr(struct axienet_local *lp, u32 count, u32 usec)
>  	return cr;
>  }
>  
> +/**
> + * axienet_cr_params() - Extract coalesce parameters from the CR

nit: axienet_coalesce_params

> + * @lp: Device private data
> + * @cr: The control register to parse
> + * @count: Number of packets before an interrupt
> + * @usec: Idle time (in usec) before an interrupt
> + */
> +static void axienet_coalesce_params(struct axienet_local *lp, u32 cr,
> +				    u32 *count, u32 *usec)
> +{
> +	u64 clk_rate = axienet_dma_rate(lp);
> +	u64 timer = FIELD_GET(XAXIDMA_DELAY_MASK, cr);
> +
> +	*count = FIELD_GET(XAXIDMA_COALESCE_MASK, cr);
> +	*usec = DIV64_U64_ROUND_CLOSEST(timer * XAXIDMA_DELAY_SCALE, clk_rate);
> +}
> +
>  /**
>   * axienet_dma_start - Set up DMA registers and start DMA operation
>   * @lp:		Pointer to the axienet_local structure