[RFC PATCH] clk: sunxi-ng: h616: Reparent CPU clock during frequency changes

[Andre Przywara]

On Sun, 10 Nov 2024 20:33:47 +0800
Chen-Yu Tsai <wens at csie.org> wrote:

Hi,

> On Sat, Nov 9, 2024 at 7:15 AM Evgeny Boger <boger at wirenboard.com> wrote:
> >
> > On 11/9/24 01:34, Andre Przywara wrote:  
> > > On Fri, 8 Nov 2024 23:14:51 +0300
> > > Evgeny Boger <boger at wirenboard.com> wrote:
> > >
> > > Hi Evgeny,
> > >  
> > >> Tested-by: Evgeny Boger <boger at wirenboard.com>
> > >>
> > >> We had stability issues with some of our T507-based boards. T507 is the
> > >> same die as H616, to my knowledge.
> > >> They were fixed by essentially the same patch, which we unfortunately
> > >> didn't submitted to mainline:
> > >> https://github.com/wirenboard/linux/commit/dc06e377108c935b2d1f5ce3d54ca1a1756458af
> > >>
> > >> It's worth noticing that not only the reparenting is mandated by T5 User
> > >> Manual (section 3.3.3.1), it's also is implemented in vendor BSP in the
> > >> same way.
> > >>
> > >> We tested the patch extensively on dozens of custom T507 boards (Wiren
> > >> Board 8 PLC). In our test it significantly improved the stability,
> > >> especially at low core voltages.  
> > > many thanks for this reply, I was hoping for such a kind of report!
> > > I typically don't test those things in anger, and only have a few
> > > boards, so having those reports from the real world is very helpful!
> > >
> > > Can you maybe give some hint on how you tested this? Does "at low core
> > > voltages" mean you forced transitions between the lower OPPs only, or
> > > were the chips undervolted?  
> > Both, in a way. Some boards (about 1 in 20 or so) would hang after a few
> > days of operation.
> >
> > During our investigation, we found they would never hang under stress
> > testing, so we started examining cpufreq-related factors.
> >
> > Disabling lower OPPs also prevented hanging. If we artificially lowered
> > the OPP voltages (undervolting the chip), the boards would hang much
> > faster without the patch, and even the previously stable ones would
> > start to hang.  
> 
> I guess we can merge this one then?

Sorry, didn't realise this was a question.

So yes, please, from my side this looks like the right to do, and Evgeny's
report supports the need for this.

So please queue this somewhere.

Cheers,
Andre
> 
> ChenYu
> 
> > >>   From my understanding, all Allwinner SoCs need to follow this kind of
> > >> procedure, however it's only implemented in mainline for a handful of chips.  
> > > Yes, I saw, I have added this to my A523 code already, and prepared a
> > > patch for the H6.
> > > Do you have boards with any other Allwinner SoCs you could test on, or
> > > even already have experience with?  
> > Unfortunately, no, not really. We only use the T507 and A40i at the moment.
> > We’ve never had these kinds of issues with the A40i, though. By the way,
> > the A40i is among the few Allwinner chips with reparenting implemented
> > in the mainline.
> >
> > The A523/T527 is really nice; it's a pity it's limited to 4GB RAM.
> >  
> > >
> > > Cheers,
> > > Andre  
> >
> > --
> > Kind regards,
> > Evgeny Boger
> >