[PATCH net-next RFC 0/5] net: phy: Introduce a port representation

[Andrew Lunn]

>   I have however seen devices that have a 1G PHY connected to a RJ45
> port with 2 lanes only, thus limiting the max achievable speed to 100M.
> Here, we would explicietly describe the port has having 2 lanes. 

Some PHYs would handle this via downshift, detecting that some pairs
are broken, and then dropping down to 100M on their own. So it is not
always necessary to have a board property, at least not for data.

I've no idea how this affects power transfer. Can the link partners
detect which pairs are actually wired?

       Andrew