[PATCH 2/2] arm64: dts: ti: k3-am62p5*/k3-j722s: Add bootph-all property to necessary nodes to enable Ethernet boot

[Roger Quadros]

On 06/01/2025 14:31, Chintan Vankar wrote:
> Ethernet boot requires CPSW nodes to be present starting from R5 SPL
> stage. Add bootph-all property to necessary nodes for CPSW to enable those
> nodes during SPL stage along with later boot stages for AM62p-SK and
> J722s.
> 
> Signed-off-by: Chintan Vankar <c-vankar at ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 3 +++
>  arch/arm64/boot/dts/ti/k3-am62p5-sk.dts                | 2 ++
>  arch/arm64/boot/dts/ti/k3-j722s-evm.dts                | 3 +++
>  3 files changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
> index 6e3beb5c2e01..96ddc5c17991 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
> @@ -50,6 +50,7 @@ phy_gmii_sel: phy at 4044 {
>  			compatible = "ti,am654-phy-gmii-sel";
>  			reg = <0x4044 0x8>;
>  			#phy-cells = <1>;
> +			bootph-all;


Shouldn't bootph-all be the first property in the DT node?

>  		};
>  
>  		epwm_tbclk: clock-controller at 4130 {
> @@ -714,6 +715,7 @@ ethernet-ports {
>  			#size-cells = <0>;
>  
>  			cpsw_port1: port at 1 {
> +				bootph-all;
>  				reg = <1>;
>  				ti,mac-only;
>  				label = "port1";
> @@ -742,6 +744,7 @@ cpsw3g_mdio: mdio at f00 {
>  			clock-names = "fck";
>  			bus_freq = <1000000>;
>  			status = "disabled";
> +			bootph-all;
>  		};
>  
>  		cpts at 3d000 {
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
> index ad71d2f27f53..28b08eb79da3 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
> @@ -226,6 +226,7 @@ main_mdio1_pins_default: main-mdio1-default-pins {
>  			AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */
>  			AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */
>  		>;
> +		bootph-all;
>  	};
>  
>  	main_mmc1_pins_default: main-mmc1-default-pins {
> @@ -495,6 +496,7 @@ &cpsw3g_mdio {
>  
>  	cpsw3g_phy0: ethernet-phy at 0 {
>  		reg = <0>;
> +		bootph-all;
>  		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>  		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>  		ti,min-output-impedance;
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> index 796287c76b69..1785c9848664 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> @@ -303,6 +303,7 @@ mdio_pins_default: mdio-default-pins {
>  			J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */
>  			J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */
>  		>;
> +		bootph-all;
>  	};
>  
>  	ospi0_pins_default: ospi0-default-pins {
> @@ -337,6 +338,7 @@ J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */
>  			J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */
>  			J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
>  		>;
> +		bootph-all;
>  	};
>  
>  	main_usb1_pins_default: main-usb1-default-pins {
> @@ -374,6 +376,7 @@ &cpsw3g_mdio {
>  
>  	cpsw3g_phy0: ethernet-phy at 0 {
>  		reg = <0>;
> +		bootph-all;
>  		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>  		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>  		ti,min-output-impedance;

-- 
cheers,
-roger