[PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[Will Deacon]

On Fri, Jan 03, 2025 at 10:16:43AM -0800, Rob Clark wrote:
> On Fri, Jan 3, 2025 at 7:37 AM Will Deacon <will at kernel.org> wrote:
> >
> > (please don't top-post...)
> >
> > On Mon, Dec 30, 2024 at 06:45:29PM +0530, Bibek Kumar Patro wrote:
> > > On 12/12/2024 8:43 PM, Bibek Kumar Patro wrote:
> > > > This patch series consist of six parts and covers the following:
> > > >
> > > > 1. Provide option to re-enable context caching to retain prefetcher
> > > >     settings during reset and runtime suspend.
> > > >
> > > > 2. Remove cfg inside qcom_smmu structure and replace it with single
> > > >     pointer to qcom_smmu_match_data avoiding replication of multiple
> > > >     members from same.
> > > >
> > > > 3. Add support for ACTLR PRR bit setup via adreno-smmu-priv interface.
> > > >
> > > > 4. Introduce intital set of driver changes to implement ACTLR register
> > > >     for custom prefetcher settings in Qualcomm SoCs.
> > > >
> > > > 5. Add ACTLR data and support for qcom_smmu_500.
> > > >
> > > > Changes in v18 from v17_RESEND:
> > > >   - 1/5 : No changes
> > > >   - 2/5 : No changes - reviewed-by tags collected
> > > >   - 3/5 : Addition of
> > > >     pm_runtime_resume_and_get()/pm_runtime_put_autosuspend()
> > > >     around register access of PRR related private interfaces
> > > >     as discussed in v17_RESEND.
> > > >   - 4/5, 5/5 : No changes - reviewed-by tags collected
> > > >   Link to v17_RESEND:
> > > >   https://lore.kernel.org/all/20241114160721.1527934-1-quic_bibekkum@quicinc.com/
> > >
> > > Thought to follow up on this thread to highlight the latest version (v18) of
> > > this series, in case it was missed during the vacation period.
> >
> >
> > I'm waiting for Rob (Clark) to ack the last patch, as he had comments on
> > the previous version.
> 
> You mean 3/5?  The latest (v18) lgtm, a-b

Sorry, yes, I meant 3/5. Thanks for having a look!

Will