[PATCH v2] arm64: dts: mediatek: mt8188: Assign apll1 clock as parent to avoid hang

[AngeloGioacchino Del Regno]

Il 07/02/25 18:41, Nícolas F. R. A. Prado ha scritto:
> Certain registers in the AFE IO space require the apll1 clock to be
> enabled in order to be read, otherwise the machine hangs (registers like
> 0x280, 0x410 (AFE_GAIN1_CON0) and 0x830 (AFE_CONN0_5)). During AFE
> driver probe, when initializing the regmap for the AFE IO space those
> registers are read, resulting in a hang during boot.
> 
> This has been observed on the Genio 700 EVK, Genio 510 EVK and
> MT8188-Geralt-Ciri Chromebook, all of which are based on the MT8188 SoC.
> 
> Assign CLK_TOP_APLL1_D4 as the parent for CLK_TOP_A1SYS_HP, which is
> enabled during register read and write, to make sure the apll1 is
> enabled during register operations and prevent the MT8188 machines from
> hanging during boot.
> 
> Cc: stable at vger.kernel.org
> Fixes: 4dbec3a59a71 ("arm64: dts: mediatek: mt8188: Add audio support")
> Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado at collabora.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

> ---
> Changes in v2:
> - Changed patch from explicitly enabling apll1 clock in the driver to
>    assigning apll1_d4 as the parent for the a1sys_hp clock in the
>    mt8188.dtsi
> - Link to v1: https://lore.kernel.org/r/20241203-mt8188-afe-fix-hang-disabled-apll1-clk-v1-1-07cdd7760834@collabora.com
> ---
>   arch/arm64/boot/dts/mediatek/mt8188.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> index 5d78f51c6183c15018986df2c76e6fdc1f9f43b4..6352c9bd436550dce66435f23653ebcb43ccf0cd 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> @@ -1392,7 +1392,7 @@ afe: audio-controller at 10b10000 {
>   			compatible = "mediatek,mt8188-afe";
>   			reg = <0 0x10b10000 0 0x10000>;
>   			assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>;
> -			assigned-clock-parents =  <&clk26m>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_APLL1_D4>;
>   			clocks = <&clk26m>,
>   				 <&apmixedsys CLK_APMIXED_APLL1>,
>   				 <&apmixedsys CLK_APMIXED_APLL2>,
> 
> ---
> base-commit: ed58d103e6da15a442ff87567898768dc3a66987
> change-id: 20241203-mt8188-afe-fix-hang-disabled-apll1-clk-b3c11782cbaf
> 
> Best regards,