[PATCH v2] arm64: dts: add cpu cache information to ExynosAuto-v920

[Krzysztof Kozlowski]

On 31/01/2025 14:27, Sudeep Holla wrote:
>>>
>> [snip]
>>  > +		l3_cache_cl0: l3-cache0 {
>> You can add one node for cl0 and cl1, say "l3_cache_cl0_cl1" and
>> Remove the specific node for CL1, because both are same.
>>
> 
> What do you mean by "both are same" ?
> Do you mean both have exact same properties but are physically different
> caches ? OR
> Do you mean it is just one shared cache ?
> 
> If former, we still need distinct node to get the cacheinfo about
> shareability correct. If this is about avoiding duplication of errors,
> you can probably define some macro and avoid it, but we need 2 nodes in
> the devicetree.
> 
> If latter, you suggestion is correct.

No answers here, so I drop this patch from my queue.

Best regards,
Krzysztof