[PATCH 1/9] dt-bindings: reset: imx95-gpu-blk-ctrl: Document Freescale i.MX95 GPU reset
Marek Vasut
marex at denx.de
Thu Feb 27 08:58:01 PST 2025
The instance of the GPU populated in Freescale i.MX95 does require
release from reset by writing into a single GPUMIX block controller
GPURESET register bit 0. Document support for this reset register.
Signed-off-by: Marek Vasut <marex at denx.de>
---
Cc: Boris Brezillon <boris.brezillon at collabora.com>
Cc: Conor Dooley <conor+dt at kernel.org>
Cc: David Airlie <airlied at gmail.com>
Cc: Fabio Estevam <festevam at gmail.com>
Cc: Krzysztof Kozlowski <krzk+dt at kernel.org>
Cc: Liviu Dudau <liviu.dudau at arm.com>
Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
Cc: Maxime Ripard <mripard at kernel.org>
Cc: Pengutronix Kernel Team <kernel at pengutronix.de>
Cc: Philipp Zabel <p.zabel at pengutronix.de>
Cc: Rob Herring <robh at kernel.org>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Sebastian Reichel <sre at kernel.org>
Cc: Shawn Guo <shawnguo at kernel.org>
Cc: Simona Vetter <simona at ffwll.ch>
Cc: Steven Price <steven.price at arm.com>
Cc: Thomas Zimmermann <tzimmermann at suse.de>
Cc: devicetree at vger.kernel.org
Cc: dri-devel at lists.freedesktop.org
Cc: imx at lists.linux.dev
Cc: linux-arm-kernel at lists.infradead.org
---
.../reset/fsl,imx95-gpu-blk-ctrl.yaml | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/fsl,imx95-gpu-blk-ctrl.yaml
diff --git a/Documentation/devicetree/bindings/reset/fsl,imx95-gpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/reset/fsl,imx95-gpu-blk-ctrl.yaml
new file mode 100644
index 0000000000000..dc701bd556c0b
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/fsl,imx95-gpu-blk-ctrl.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/fsl,imx95-gpu-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX95 GPU Block Controller
+
+maintainers:
+ - Marek Vasut <marex at denx.de>
+
+description: |
+ This reset controller is a block of ad-hoc debug registers, one of
+ which is a single-bit GPU reset.
+
+properties:
+ compatible:
+ - const: fsl,imx95-gpu-blk-ctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - power-domains
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ reset-controller at 4d810000 {
+ compatible = "fsl,imx95-gpu-blk-ctrl";
+ reg = <0x0 0x4d810000 0x0 0xc>;
+ clocks = <&scmi_clk IMX95_CLK_GPUAPB>;
+ power-domains = <&scmi_devpd IMX95_PD_GPU>;
+ #reset-cells = <1>;
+ };
--
2.47.2
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