[PATCH v4 1/2] dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188
AngeloGioacchino Del Regno
angelogioacchino.delregno at collabora.com
Mon Feb 24 00:42:15 PST 2025
Il 21/02/25 08:50, Friday Yang ha scritto:
> On the MediaTek platform, some SMI LARBs are directly connected to
> the SMI Common, while others are connected to the SMI Sub-Common,
> which in turn is connected to the SMI Common. The hardware block
> diagram can be described as follows.
>
> SMI-Common(Smart Multimedia Interface Common)
> |
> +----------------+------------------+
> | | |
> | | |
> | | |
> | | |
> | | |
> larb0 SMI-Sub-Common0 SMI-Sub-Common1
> | | | | |
> larb1 larb2 larb3 larb7 larb9
>
> For previous discussion on the direction of the code modifications,
> please refer to:
> https://lore.kernel.org/all/CAFGrd9qZhObQXvm2_abqaX83xMLqxjQETB2=
> wXpobDWU1CnvkA at mail.gmail.com/
> https://lore.kernel.org/all/CAPDyKFpokXV2gJDgowbixTvOH_5VL3B5H8ey
> hP+KJ5Fasm2rFg at mail.gmail.com/
>
> On the MediaTek MT8188 SoC platform, we encountered power-off failures
> and SMI bus hang issues during camera stress tests. The issue arises
> because bus glitches are sometimes produced when MTCMOS powers on or
> off. While this is fairly normal, the software must handle these
> glitches to avoid mistaking them for transaction signals. What's
> more, this issue emerged only after the initial upstreaming of this
> binding. Without these patches, the SMI becomes unstable during camera
> stress tests.
>
> The software solutions can be summarized as follows:
>
> 1. Use CLAMP to disable the SMI sub-common port after turning off the
> LARB CG and before turning off the LARB MTCMOS.
> 2. Use CLAMP to disable/enable the SMI sub-common port.
> 3. Implement an AXI reset for SMI LARBs.
>
> This patch add '#reset-cells' for the clock controller located in image,
> camera and IPE subsystems.
>
> Signed-off-by: Friday Yang <friday.yang at mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> ---
> .../bindings/clock/mediatek,mt8188-clock.yaml | 21 +++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
> index 860570320545..2985c8c717d7 100644
> --- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
> @@ -57,6 +57,27 @@ required:
> - reg
> - '#clock-cells'
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - mediatek,mt8188-camsys-rawa
> + - mediatek,mt8188-camsys-rawb
> + - mediatek,mt8188-camsys-yuva
> + - mediatek,mt8188-camsys-yuvb
> + - mediatek,mt8188-imgsys-wpe1
> + - mediatek,mt8188-imgsys-wpe2
> + - mediatek,mt8188-imgsys-wpe3
> + - mediatek,mt8188-imgsys1-dip-nr
> + - mediatek,mt8188-imgsys1-dip-top
> + - mediatek,mt8188-ipesys
> +
> + then:
> + required:
> + - '#reset-cells'
> +
> additionalProperties: false
>
> examples:
> --
> 2.46.0
>
--
AngeloGioacchino Del Regno
Senior Software Engineer
Collabora Ltd.
Platinum Building, St John's Innovation Park, Cambridge CB4 0DS, UK
Registered in England & Wales, no. 5513718
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