[PATCH v5 -next 07/11] PCI: brcmstb: Adjust PHY PLL setup to use a 54MHz input refclk

[Stanimir Varbanov]

Hi Bjorn,

On 2/21/25 11:33 PM, Bjorn Helgaas wrote:
> On Mon, Jan 20, 2025 at 03:01:15PM +0200, Stanimir Varbanov wrote:
>> The default input reference clock for the PHY PLL is 100Mhz, except for
>> some devices where it is 54Mhz like bcm2712C1 and bcm2712D0.
>>
>> To implement this adjustments introduce a new .post_setup op in
>> pcie_cfg_data and call it at the end of brcm_pcie_setup function.
>>
>> The bcm2712 .post_setup callback implements the required MDIO writes that
>> switch the PLL refclk and also change PHY PM clock period.
>>
>> Without this RPi5 PCIex1 is unable to enumerate endpoint devices on
>> the expansion connector.
> 
> This makes it sound like this patch should be reordered before "[PATCH
> v5 -next 06/11] PCI: brcmstb: Add bcm2712 support".
> 
> We don't really want a driver to claim a bcm2712 controller before
> it's able to enumerate devices, because that would break bisection
> through this.

I absolutely agree with you in regards to bisect-ability. But to satisfy
this I have to squash "Adjust PHY PLL ..." into "PCI: brcmstb: Add
bcm2712 support" to avoid a warning about not used function. If that
works I'll send a new rebased controller/brcmstb version (v6).

~Stan