[PATCH] arm64: dts: imx8mp: configure GPU and NPU clocks to overdrive rate

[Shawn Guo]

On Tue, Feb 04, 2025 at 07:27:37PM +0100, Lucas Stach wrote:
> A lot of other clocks on the i.MX8MP, including the DRAM set up by the
> bootloader are already running at overdrive clock rates. While this is a
> deviation from the configuration of other i.MX8M* family SoCs, overdrive
> is the default for most i.MX8MP boards and only some special purpose
> boards will choose to run the SoC at nominal drive rates.

Are any of these special purpose boards in upstream?  If so, does this
change have any impact on them?

Shawn

> Up the GPU and
> NPU clock rates to their overdrive level to be consistent with other
> clocks set up in the dtsi.
> 
> Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
> ---
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index e0d3b8cba221..aeaa6a5c2f56 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -816,12 +816,12 @@ pgc_mlmix: power-domain at 4 {
>  						assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
>  								  <&clk IMX8MP_CLK_ML_AXI>,
>  								  <&clk IMX8MP_CLK_ML_AHB>;
> -						assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
> +						assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
>  									 <&clk IMX8MP_SYS_PLL1_800M>,
>  									 <&clk IMX8MP_SYS_PLL1_800M>;
> -						assigned-clock-rates = <800000000>,
> +						assigned-clock-rates = <1000000000>,
>  								       <800000000>,
> -								       <300000000>;
> +								       <400000000>;
>  					};
>  
>  					pgc_audio: power-domain at 5 {
> @@ -2232,9 +2232,9 @@ gpu3d: gpu at 38000000 {
>  			clock-names = "core", "shader", "bus", "reg";
>  			assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
>  					  <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
> -			assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
> -						 <&clk IMX8MP_SYS_PLL1_800M>;
> -			assigned-clock-rates = <800000000>, <800000000>;
> +			assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
> +						 <&clk IMX8MP_SYS_PLL2_1000M>;
> +			assigned-clock-rates = <1000000000>, <1000000000>;
>  			power-domains = <&pgc_gpu3d>;
>  		};
>  
> @@ -2247,8 +2247,8 @@ gpu2d: gpu at 38008000 {
>  				 <&clk IMX8MP_CLK_GPU_AHB>;
>  			clock-names = "core", "bus", "reg";
>  			assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
> -			assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
> -			assigned-clock-rates = <800000000>;
> +			assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
> +			assigned-clock-rates = <1000000000>;
>  			power-domains = <&pgc_gpu2d>;
>  		};
>  
> 
> base-commit: 2014c95afecee3e76ca4a56956a936e23283f05b
> -- 
> 2.39.5
>