[PATCH v2 01/14] arm64: cpufeature: Handle NV_frac as a synonym of NV2

[Joey Gouly]

On Thu, Feb 20, 2025 at 01:48:54PM +0000, Marc Zyngier wrote:
> With ARMv9.5, an implementation supporting Nested Virtualization
> is allowed to only support NV2, and to avoid supporting the old
> (and useless) ARMv8.3 variant.
> 
> This is indicated by ID_AA64MMFR2_EL1.NV being 0 (as if NV wasn't
> implemented) and ID_AA64MMDR4_EL1.NV_frac being 1 (indicating that

typo: ID_AA64MMDR4_EL1 -> ID_AA64MMFR4_EL1

> NV2 is actually supported).
> 
> Given that KVM only deals with NV2 and refuses to use the old NV,
> detecting NV2 or NV_frac is what we need to enable it.
> 
> Signed-off-by: Marc Zyngier <maz at kernel.org>
> ---
>  arch/arm64/kernel/cpufeature.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index d561cf3b8ac7b..2c198cd4f9405 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -497,6 +497,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = {
>  
>  static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = {
>  	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0),
> +	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0),
>  	ARM64_FTR_END,
>  };
>  
> @@ -2162,7 +2163,7 @@ static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap,
>  	if (kvm_get_mode() != KVM_MODE_NV)
>  		return false;
>  
> -	if (!has_cpuid_feature(cap, scope)) {
> +	if (!cpucap_multi_entry_cap_matches(cap, scope)) {
>  		pr_warn("unavailable: %s\n", cap->desc);
>  		return false;
>  	}
> @@ -2519,7 +2520,17 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
>  		.capability = ARM64_HAS_NESTED_VIRT,
>  		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
>  		.matches = has_nested_virt_support,
> -		ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2)
> +		.match_list = (const struct arm64_cpu_capabilities []){
> +			{
> +				.matches = has_cpuid_feature,
> +				ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2)
> +			},
> +			{
> +				.matches = has_cpuid_feature,
> +				ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY)
> +			},
> +			{ /* Sentinel */ }
> +		},
>  	},
>  	{
>  		.capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
> -- 
> 2.39.2
>