[PATCH 5/6] arm64: dts: rockchip: Add thermal trim OTP and tsadc nodes

[Sebastian Reichel]

Hi,

On Sun, Feb 16, 2025 at 12:34:54AM +0100, Nicolas Frattaroli wrote:
> Thanks to Heiko's work getting OTP working on the RK3576, we can specify
> the thermal sensor trim values which are stored there now, and with my
> driver addition to rockchip_thermal, we can make use of these.
> 
> Add them to the devicetree for the SoC.
> 
> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli at collabora.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3576.dtsi | 75 ++++++++++++++++++++++++++++++++
>  1 file changed, 75 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> index 73df515a3937414d89515b4ddccf71f33f6a4fe7..c55d7096a3e985d48240c2cab3de572b9ece2b23 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> @@ -1441,6 +1441,48 @@ gpu_leakage: gpu-leakage at 21 {
>  			log_leakage: log-leakage at 22 {
>  				reg = <0x22 0x1>;
>  			};
> +			bigcore_tsadc_trim_l: bigcore-tsadc-trim-l at 24 {
> +				reg = <0x24 0x1>;
> +			};
> +			bigcore_tsadc_trim_h: bigcore-tsadc-trim-h at 25 {
> +				reg = <0x25 0x1>;
> +				bits = <0 2>;
> +			};

Looks like TRIM-L and TRIM-H are always consecutive and even for
Rockchip it would be weird to change that in the future. So I
think you can simplify this:

bigcore_tsadc_trim: bigcore-tsadc-trim at 24 {
    reg = <0x24 0x2>;
    bits = <0 10>;
};

That looks much cleaner IMHO and should also simplify the driver and
the binding a bit :)

Greetings,

-- Sebastian

> +			litcore_tsadc_trim_l: litcore-tsadc-trim-l at 26 {
> +				reg = <0x26 0x1>;
> +			};
> +			litcore_tsadc_trim_h: litcore-tsadc-trim-h at 27 {
> +				reg = <0x27 0x1>;
> +				bits = <0 2>;
> +			};
> +			ddr_tsadc_trim_l: ddr-tsadc-trim-l at 28 {
> +				reg = <0x28 0x1>;
> +			};
> +			ddr_tsadc_trim_h: ddr-tsadc-trim-h at 29 {
> +				reg = <0x29 0x1>;
> +				bits = <0 2>;
> +			};
> +			npu_tsadc_trim_l: npu-tsadc-trim-l at 2a {
> +				reg = <0x2a 0x1>;
> +			};
> +			npu_tsadc_trim_h: npu-tsadc-trim-h at 2b {
> +				reg = <0x2b 0x1>;
> +				bits = <0 2>;
> +			};
> +			gpu_tsadc_trim_l: gpu-tsadc-trim-l at 2c {
> +				reg = <0x2c 0x1>;
> +			};
> +			gpu_tsadc_trim_h: gpu-tsadc-trim-h at 2d {
> +				reg = <0x2d 0x1>;
> +				bits = <0 2>;
> +			};
> +			soc_tsadc_trim_l: soc-tsadc-trim-l at 64 {
> +				reg = <0x64 0x1>;
> +			};
> +			soc_tsadc_trim_h: soc-tsadc-trim-h at 65 {
> +				reg = <0x65 0x1>;
> +				bits = <0 2>;
> +			};
>  		};
>  
>  		gic: interrupt-controller at 2a701000 {
> @@ -1852,6 +1894,39 @@ tsadc: tsadc at 2ae70000 {
>  			rockchip,hw-tshut-temp = <120000>;
>  			rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
>  			rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			tsadc at 0 {
> +				reg = <0>;
> +				nvmem-cells = <&soc_tsadc_trim_l>, <&soc_tsadc_trim_h>;
> +				nvmem-cell-names = "trim_l", "trim_h";
> +			};
> +			tsadc at 1 {
> +				reg = <1>;
> +				nvmem-cells = <&bigcore_tsadc_trim_l>, <&bigcore_tsadc_trim_h>;
> +				nvmem-cell-names = "trim_l", "trim_h";
> +			};
> +			tsadc at 2 {
> +				reg = <2>;
> +				nvmem-cells = <&litcore_tsadc_trim_l>, <&litcore_tsadc_trim_h>;
> +				nvmem-cell-names = "trim_l", "trim_h";
> +			};
> +			tsadc at 3 {
> +				reg = <3>;
> +				nvmem-cells = <&ddr_tsadc_trim_l>, <&ddr_tsadc_trim_h>;
> +				nvmem-cell-names = "trim_l", "trim_h";
> +			};
> +			tsadc at 4 {
> +				reg = <4>;
> +				nvmem-cells = <&npu_tsadc_trim_l>, <&npu_tsadc_trim_h>;
> +				nvmem-cell-names = "trim_l", "trim_h";
> +			};
> +			tsadc at 5 {
> +				reg = <5>;
> +				nvmem-cells = <&gpu_tsadc_trim_l>, <&gpu_tsadc_trim_h>;
> +				nvmem-cell-names = "trim_l", "trim_h";
> +			};
>  		};
>  
>  		i2c9: i2c at 2ae80000 {
> 
> -- 
> 2.48.1
> 
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