[Q] Frequency & duty cycle measurement?
Dipen Patel
dipenp at nvidia.com
Wed Feb 19 14:32:56 PST 2025
On 1/21/25 7:19 AM, Csókás Bence wrote:
> he hardware is capable of taking a snapshot of the timer value into another
> dedicated register pair (RA, RB) on the rising/falling edges, and a small
> `devmem`-based userspace utility was created as a working PoC
I am late to the party :) Seems above statement looks lot like what HTE
subsystem is doing. Right now, only userspace path is through the gpiolib
due to usage that time was limited to GPIOs. However, we can extend HTE to meet
this scenario.
Thanks,
Best Regards,
Dipen Patel
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