[PATCH net-next 9/9] net: stmmac: convert to phylink managed EEE support
Jon Hunter
jonathanh at nvidia.com
Wed Feb 19 12:05:57 PST 2025
On 19/02/2025 19:13, Russell King (Oracle) wrote:
> On Wed, Feb 19, 2025 at 05:52:34PM +0000, Jon Hunter wrote:
>> On 19/02/2025 15:36, Russell King (Oracle) wrote:
>>> So clearly the phylink resolver is racing with the rest of the stmmac
>>> resume path - which doesn't surprise me in the least. I believe I raised
>>> the fact that calling phylink_resume() before the hardware was ready to
>>> handle link-up is a bad idea precisely because of races like this.
>>>
>>> The reason stmmac does this is because of it's quirk that it needs the
>>> receive clock from the PHY in order for stmmac_reset() to work.
>>
>> I do see the reset fail infrequently on previous kernels with this device
>> and when it does I see these messages ...
>>
>> dwc-eth-dwmac 2490000.ethernet: Failed to reset the dma
>> dwc-eth-dwmac 2490000.ethernet eth0: stmmac_hw_setup: DMA engine
>> initialization failed
>
> I wonder whether it's also racing with phylib, but phylink_resume()
> calling phylink_start() going in to call phy_start() is all synchronous.
> That causes __phy_resume() to be called.
>
> Which PHY device/driver is being used?
Looks like it is this Broadcom driver ...
Broadcom BCM89610 stmmac-0:00: phy_eee_rx_clock_stop: clk_stop_enable 1
Thanks
Jon
--
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