[PATCH 7/8] arm64: dts: allwinner: rg35xx: Enable LCD output
Ryan Walklin
ryan at testtoast.com
Sun Feb 16 01:27:14 PST 2025
The RG35XX has a 640x480 RGB/SPI LCD panel, supported by the SoC display
pipeline and an NV3052C controller. The H616 SOC's GPIO bank D contains
the muxed display pins for RGB and LVDS output support.
Enable the display engine and LCD timing controller, configure the
panel, and add a fixed 3.3v GPIO-controlled regulator for the panel, and
a VCC supply for the display pins as per the other GPIO banks.
Signed-off-by: Ryan Walklin <ryan at testtoast.com>
---
.../sun50i-h700-anbernic-rg35xx-2024.dts | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
index a231abf1684ad..388487d4720e2 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
@@ -175,6 +175,49 @@ reg_vcc5v: regulator-vcc5v { /* USB-C power input */
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ reg_lcd: regulator-gpio-lcd-vdd {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vdd-lcd";
+ gpio = <&pio 8 15 GPIO_ACTIVE_HIGH>; // PI15
+ enable-active-high;
+ };
+
+ spi_lcd: spi {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sck-gpios = <&pio 8 9 GPIO_ACTIVE_HIGH>; // PI9
+ mosi-gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>; // PI10
+ cs-gpios = <&pio 8 8 GPIO_ACTIVE_HIGH>; // PI8
+ num-chipselects = <1>;
+
+ panel: panel at 0 {
+ compatible = "anbernic,rg35xx-plus-panel";
+
+ reg = <0>;
+
+ spi-max-frequency = <3125000>;
+ spi-3wire;
+
+ reset-gpios = <&pio 8 14 GPIO_ACTIVE_LOW>; // PI14
+
+ backlight = <&backlight>;
+ power-supply = <®_lcd>;
+
+ pinctrl-0 = <&lcd0_rgb888_pins>;
+ pinctrl-names = "default";
+
+ port {
+ panel_in_rgb: endpoint {
+ remote-endpoint = <&tcon_lcd0_out_lcd>;
+ };
+ };
+ };
+ };
};
&codec {
@@ -187,6 +230,10 @@ &cpu0 {
cpu-supply = <®_dcdc1>;
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -206,6 +253,7 @@ &ohci0 {
&pio {
vcc-pa-supply = <®_cldo3>;
vcc-pc-supply = <®_cldo3>;
+ vcc-pd-supply = <®_cldo3>;
vcc-pe-supply = <®_cldo3>;
vcc-pf-supply = <®_cldo3>;
vcc-pg-supply = <®_aldo4>;
@@ -355,3 +403,13 @@ &usbotg {
&usbphy {
status = "okay";
};
+
+&tcon_lcd0 {
+ status = "okay";
+};
+
+&tcon_lcd0_out {
+ tcon_lcd0_out_lcd: endpoint at 1 {
+ remote-endpoint = <&panel_in_rgb>;
+ };
+};
--
2.48.1
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