[PATCH v2 1/4] cpufreq: mediatek: CCI support SoC , the transition_delay set to 10 ms

[Chun-Jen Tseng (曾俊仁)]

On Thu, 2024-11-14 at 11:22 +0100, AngeloGioacchino Del Regno wrote:

hi Angelo,

Thanks your review and recommendation.

I will fix this issue on next patch.

BRs,

Mark Tseng

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> Il 08/11/24 07:39, Mark Tseng ha scritto:
> > SoC with CCI architecture should set transition_delay to 10 ms
> > because
> > cpufreq need to call devfreq notifier in async mode. if delay less
> > than
> > 10 ms, it may get wrong OPP-level in devfreq passive governor.
> > 
> 
> This means that MediaTek SoCs can change their CPU frequency once
> every
> 10 milliseconds?!?!?!
> 
> I don't think that's really the case.
> 
> Besides, are you aware that this will have a *huge* impact on either
> power
> consumption or performance?
> We're going from a bunch of microseconds to *multiple* milliseconds
> here.
> 
> Regards,
> Angelo
>