[PATCH v10 4/4] arm64: dt: imx95: Add the missed ref clock for PCIe[0,1]

[Shawn Guo]

On Thu, Dec 11, 2025 at 02:48:21PM +0800, Richard Zhu wrote:
> i.MX95 PCIes have two reference clock inputs, one of them is from
> internal PLL. It's wired inside chip and present as "ref" clock. It's
> not an optional clock.
> 
> Add the missed ref clock for PCIe[0,1].
> 
> Signed-off-by: Richard Zhu <hongxing.zhu at nxp.com>

It doesn't seem to apply to my tree.

Shawn

> ---
>  .../boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
> index 5b6b2bb80b288..1258fcb54681e 100644
> --- a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
> +++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
> @@ -237,8 +237,9 @@ &pcie0 {
>  	clocks = <&scmi_clk IMX95_CLK_HSIO>,
>  		 <&pcieclk 1>,
>  		 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> -		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> -	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> +		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
> +		 <&hsio_blk_ctl 0>;
> +	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
>  	reset-gpio = <&expander2 9 GPIO_ACTIVE_LOW>;
>  	status = "okay";
>  };
> @@ -250,8 +251,9 @@ &pcie1 {
>  	clocks = <&scmi_clk IMX95_CLK_HSIO>,
>  		 <&pcieclk 0>,
>  		 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> -		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> -	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> +		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
> +		 <&hsio_blk_ctl 0>;
> +	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
>  	reset-gpio = <&expander2 10 GPIO_ACTIVE_LOW>;
>  	status = "okay";
>  };
> -- 
> 2.37.1
>