[arm-platforms:kvm-arm64/gicv5-full 80/82] arch/arm64/kvm/vgic/vgic-its-v5.c:1213:2-8: preceding lock on line 1181 (fwd)
Julia Lawall
julia.lawall at inria.fr
Tue Dec 23 05:05:47 PST 2025
Pleas check whether unlocks are needed at line 1213.
julia
---------- Forwarded message ----------
Date: Tue, 23 Dec 2025 20:39:59 +0800
From: kernel test robot <lkp at intel.com>
To: oe-kbuild at lists.linux.dev
Cc: lkp at intel.com, Julia Lawall <julia.lawall at inria.fr>
Subject: [arm-platforms:kvm-arm64/gicv5-full 80/82]
arch/arm64/kvm/vgic/vgic-its-v5.c:1213:2-8: preceding lock on line 1181
BCC: lkp at intel.com
CC: oe-kbuild-all at lists.linux.dev
CC: linux-arm-kernel at lists.infradead.org
TO: Sascha Bischoff <sascha.bischoff at arm.com>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git kvm-arm64/gicv5-full
head: 1426b88096b597395df4c82f089b87c62bab45da
commit: e01f1868ec7bf5d212cd8daf67da77fc8c1cd320 [80/82] KVM: arm64: gic-v5: Implement has/set/get attr for ITS MMIO regions
:::::: branch date: 4 days ago
:::::: commit date: 4 days ago
config: arm64-randconfig-r064-20251223 (https://download.01.org/0day-ci/archive/20251223/202512232029.FJOH3tvX-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 15.1.0
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Reported-by: Julia Lawall <julia.lawall at inria.fr>
| Closes: https://lore.kernel.org/r/202512232029.FJOH3tvX-lkp@intel.com/
cocci warnings: (new ones prefixed by >>)
>> arch/arm64/kvm/vgic/vgic-its-v5.c:1213:2-8: preceding lock on line 1181
arch/arm64/kvm/vgic/vgic-its-v5.c:1213:2-8: preceding lock on line 1188
vim +1213 arch/arm64/kvm/vgic/vgic-its-v5.c
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1167
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1168 static int vgic_v5_its_attr_regs_access(struct kvm_device *dev,
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1169 struct kvm_device_attr *attr,
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1170 u64 *reg, bool is_write)
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1171 {
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1172 const struct vgic_register_region *region;
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1173 struct vgic_v5_its *its;
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1174 gpa_t addr, offset;
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1175 unsigned int len;
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1176 int align, ret = 0;
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1177
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1178 its = dev->private;
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1179 offset = attr->attr;
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1180
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 @1181 mutex_lock(&dev->kvm->lock);
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1182
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1183 if (kvm_trylock_all_vcpus(dev->kvm)) {
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1184 mutex_unlock(&dev->kvm->lock);
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1185 return -EBUSY;
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1186 }
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1187
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1188 mutex_lock(&dev->kvm->arch.config_lock);
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1189
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1190 if (IS_VGIC_ADDR_UNDEF(its->vgic_v5_its_base)) {
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1191 ret = -ENXIO;
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1192 goto out;
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1193 }
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1194
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1195 region = vgic_find_mmio_region(vgic_v5_its_registers,
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1196 ARRAY_SIZE(vgic_v5_its_registers),
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1197 offset);
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1198 if (!region) {
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1199 ret = -ENXIO;
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1200 goto out;
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1201 }
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1202
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1203 /*
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1204 * Although the spec supports upper/lower 32-bit accesses to
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1205 * 64-bit ITS registers, the userspace ABI requires 64-bit
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1206 * accesses to all 64-bit wide registers. We therefore only
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1207 * support 32-bit accesses to 32-bit-wide registers.
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1208 */
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1209 align = region->access_flags & VGIC_ACCESS_64bit ? 0x7 : 0x3;
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1210 len = region->access_flags & VGIC_ACCESS_64bit ? 8 : 4;
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1211
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1212 if (offset & align)
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 @1213 return -EINVAL;
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1214
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1215 addr = its->vgic_v5_its_base + offset;
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1216
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1217 if (is_write) {
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1218 region->its_write(dev->kvm, its, addr, len, *reg);
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1219 } else {
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1220 *reg = region->its_read(dev->kvm, its, addr, len);
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1221 }
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1222 out:
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1223 mutex_unlock(&dev->kvm->arch.config_lock);
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1224 kvm_unlock_all_vcpus(dev->kvm);
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1225 mutex_unlock(&dev->kvm->lock);
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1226
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1227 return ret;
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1228 }
e01f1868ec7bf5 Sascha Bischoff 2025-09-05 1229
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