[arm-platforms:kvm-arm64/gicv5-full 48/82] arch/arm64/kvm/vgic/vgic-v5.c:737:26: warning: variable 'd' set but not used
kernel test robot
lkp at intel.com
Mon Dec 22 08:50:04 PST 2025
tree: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git kvm-arm64/gicv5-full
head: 1426b88096b597395df4c82f089b87c62bab45da
commit: 784f082a09f253879e4c4f57182b3a7e0bb92539 [48/82] KVM: arm64: gic-v5: Init/tear down VMTEs
config: arm64-randconfig-003-20251222 (https://download.01.org/0day-ci/archive/20251223/202512230041.45OmXxwl-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 11.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251223/202512230041.45OmXxwl-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512230041.45OmXxwl-lkp@intel.com/
All warnings (new ones prefixed by >>):
arch/arm64/kvm/vgic/vgic-v5.c: In function 'vgic_v5_init':
>> arch/arm64/kvm/vgic/vgic-v5.c:737:26: warning: variable 'd' set but not used [-Wunused-but-set-variable]
737 | struct irq_data *d;
| ^
At top level:
arch/arm64/kvm/vgic/vgic-v5.c:174:12: warning: 'vgic_v5_irs_assign_vmt' defined but not used [-Wunused-function]
174 | static int vgic_v5_irs_assign_vmt(bool two_level, u8 vm_id_bits, phys_addr_t vmt_base)
| ^~~~~~~~~~~~~~~~~~~~~~
vim +/d +737 arch/arm64/kvm/vgic/vgic-v5.c
722
723 /*
724 * Claim and populate a VMTE (optionally making a new L2 VMT valid), create VPE
725 * doorbells, allocate VPET and populate for each VPE. Finally, we also init the
726 * vIRS, which means allocating and making the virtual SPI IST valid.
727 *
728 * Note: We do need to put the cart before the horse here. The VPE doorbells are
729 * our conduit for communication with the IRS, which means we need to have those
730 * before making the VMTE valid.
731 */
732 int vgic_v5_init(struct kvm *kvm)
733 {
734 int nr_vcpus, ret = 0;
735 struct kvm_vcpu *vcpu, *vcpu0;
736 unsigned long i;
> 737 struct irq_data *d;
738 unsigned int db_virq;
739
740 if (!vgic_v5_vmt_allocated()) {
741 pr_err("No VM tables allocated; something is horribly wrong\n");
742 return -ENODEV;
743 }
744
745 kvm_for_each_vcpu(i, vcpu, kvm) {
746 if (vcpu_has_nv(vcpu)) {
747 kvm_err("Nested GICv5 VMs are currently unsupported\n");
748 return -EINVAL;
749 }
750 }
751 nr_vcpus = atomic_read(&kvm->online_vcpus);
752 if (WARN_ON(nr_vcpus == 0)) {
753 ret = -ENODEV;
754 goto fail;
755
756 }
757 kvm->arch.vgic.gicv5_vm.nr_vpes = nr_vcpus;
758
759 /*
760 * We only allow userspace to drive the SW_PPI, if it is
761 * implemented.
762 */
763 kvm->arch.vgic.gicv5_vm.userspace_ppis[0] = GICV5_SW_PPI & GICV5_HWIRQ_ID;
764 kvm->arch.vgic.gicv5_vm.userspace_ppis[0] &= ppi_caps->impl_ppi_mask[0];
765 kvm->arch.vgic.gicv5_vm.userspace_ppis[1] = 0;
766
767 ret = vgic_v5_allocate_vm_id(kvm);
768 if (ret)
769 goto fail;
770
771 if (vgic_v5_create_per_vm_domain(&kvm->arch.vgic.gicv5_vm))
772 goto fail_cleanup_id;
773
774 /*
775 * Allocate VPE doorbells first - these are our conduit for
776 * communicating with the host irqchip driver. Can't do any earlier as
777 * we wouldn't know the VM ID.
778 */
779 db_virq = irq_domain_alloc_irqs(kvm->arch.vgic.gicv5_vm.domain,
780 nr_vcpus, NUMA_NO_NODE,
781 &kvm->arch.vgic.gicv5_vm);
782 if (db_virq < 0) {
783 ret = db_virq;
784 goto fail_cleanup_domain;
785 }
786 kvm->arch.vgic.gicv5_vm.vpe_db_base = db_virq;
787
788 kvm_for_each_vcpu(i, vcpu, kvm) {
789 d = irq_domain_get_irq_data(kvm->arch.vgic.gicv5_vm.domain,
790 db_virq + i);
791 irq_set_status_flags(db_virq + i, IRQ_NOAUTOEN);
792
793 ret = request_irq(db_virq + i, db_handler, 0, "vcpu", vcpu);
794 if (ret)
795 goto fail_cleanup_partial_dbs;
796
797 /* Stash it with the VCPU for easy retrieval */
798 vcpu->arch.vgic_cpu.vgic_v5.gicv5_vpe.db = db_virq + i;
799 }
800
801 /* Populate VMTE (with VPET and VM descriptor) */
802 ret = vgic_v5_vmte_init(kvm);
803 if (ret)
804 goto fail_cleanup_dbs;
805
806 /* We pick the first vcpu to make the VMTE valid - any would do */
807 vcpu0 = kvm_get_vcpu(kvm, 0);
808 ret = vgic_v5_send_command(vcpu0, VMTE_MAKE_VALID);
809 if (ret)
810 goto fail_cleanup_vmte;
811
812 /* Loop over all VPEs, allocate/populate their data structures */
813 kvm_for_each_vcpu(i, vcpu, kvm) {
814 ret = vgic_v5_vmte_alloc_vpe(vcpu);
815 if (ret)
816 goto fail_cleanup_vpes;
817 }
818
819 return ret;
820
821 fail_cleanup_vpes:
822 /* i contains the first vCPU that failed */
823 if (i == 0)
824 goto fail_cleanup_vmte;
825
826 do {
827 vcpu = kvm_get_vcpu(kvm, --i);
828 vgic_v5_vmte_free_vpe(vcpu);
829 } while (i != 0);
830
831 fail_cleanup_vmte:
832 vgic_v5_vmte_release(kvm);
833
834 fail_cleanup_dbs:
835 i = nr_vcpus;
836 fail_cleanup_partial_dbs:
837 /* i contains the first vCPU that failed */
838 if (i == 0)
839 goto fail_cleanup_domain;
840
841 do {
842 vcpu = kvm_get_vcpu(kvm, --i);
843 vgic_v5_disable_vcpu(vcpu);
844 } while (i != 0);
845
846 fail_cleanup_domain:
847 vgic_v5_teardown_per_vm_domain(&kvm->arch.vgic.gicv5_vm);
848
849 fail_cleanup_id:
850 vgic_v5_release_vm_id(kvm);
851
852 fail:
853 return ret;
854 }
855
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