[PATCH v8 5/7] iommu/arm-smmu-v3: Populate smmu_domain->invs when attaching masters

Nicolin Chen nicolinc at nvidia.com
Fri Dec 19 11:00:20 PST 2025


On Fri, Dec 19, 2025 at 02:56:05PM -0400, Jason Gunthorpe wrote:
> On Fri, Dec 19, 2025 at 10:54:15AM -0800, Nicolin Chen wrote:
> > On Fri, Dec 19, 2025 at 11:51:51AM -0400, Jason Gunthorpe wrote:
> > > On Wed, Dec 17, 2025 at 03:24:30PM -0800, Nicolin Chen wrote:
> > > > +	*cur = inv;
> > > > +	switch (type) {
> > > > +	case INV_TYPE_S1_ASID:
> > > > +		if (master->smmu->features & ARM_SMMU_FEAT_E2H) {
> > > > +			cur->size_opcode = CMDQ_OP_TLBI_EL2_VA;
> > > > +			cur->nsize_opcode = CMDQ_OP_TLBI_EL2_ASID;
> > > > +		} else {
> > > > +			cur->size_opcode = CMDQ_OP_TLBI_NH_VA;
> > > > +			cur->nsize_opcode = CMDQ_OP_TLBI_NH_ASID;
> > > 
> > > There is a tricky little gotcha here that probably requires a comment.
> > > 
> > > NH_VA and NH_ASID both take (VMID,ASID) as input since the ASID is
> > > always scoped to a single VMID.
> > > 
> > > In this case the invalidation logic always wires the VMID to zero,
> > > which is also the VMID the driver uses for S1 tables when the S2 is in
> > > bypass.
> > > 
> > > Which is fine, we don't support an actual S1 table on top of a S2
> > > table where we issue invalidations through the invs array.
> > > 
> > > So maybe:
> > > 
> > >  For S1 page tables the driver always uses VMID=0, and the
> > >  invalidation logic for this type will set it as well.
> > 
> > Ack. And I will drop that ssid too.
> 
> It looks like the ssid is needed for ats:
> 
> @@ -3156,12 +3162,136 @@ arm_smmu_master_build_inv(struct arm_smmu_master *master,
>         case INV_TYPE_ATS:
>         case INV_TYPE_ATS_FULL:
>                 cur->size_opcode = cur->nsize_opcode = CMDQ_OP_ATC_INV;
> +               cur->ssid = ssid;
>                 break;

Oh, right. I'll fix this.

Thanks
Nicolin



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